31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x5 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (addc SI rn imm12 cbit)) (if (eq f-rd 15) (sequence () (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr))) (set pc result)) (sequence () (if set-cc? (sequence ((SI result)) (set result (addc SI rn imm12 cbit)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rn imm12 cbit)) (set vbit (add-oflag SI rn imm12 cbit)))) (set rd result))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x5 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set temp-op1 rn) (set temp-op2 operand2) (set result (addc SI rn operand2 cbit)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (addc SI temp-op1 temp-op2 cbit)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI temp-op1 temp-op2 cbit)) (set vbit (add-oflag SI temp-op1 temp-op2 cbit)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x5 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set temp-op1 rn) (set temp-op2 operand2) (set result (addc SI rn operand2 cbit)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (addc SI temp-op1 temp-op2 cbit)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI temp-op1 temp-op2 cbit)) (set vbit (add-oflag SI temp-op1 temp-op2 cbit)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x4 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (add SI rn imm12)) (if (eq f-rd 15) (sequence () (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr))) (set pc result)) (sequence () (if set-cc? (sequence ((SI result)) (set result (addc SI rn imm12 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rn imm12 0)) (set vbit (add-oflag SI rn imm12 0)))) (set rd result))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x4 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set temp-op1 rn) (set temp-op2 operand2) (set result (add SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (addc SI temp-op1 temp-op2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI temp-op1 temp-op2 0)) (set vbit (add-oflag SI temp-op1 temp-op2 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x4 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set temp-op1 rn) (set temp-op2 operand2) (set result (add SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (addc SI temp-op1 temp-op2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI temp-op1 temp-op2 0)) (set vbit (add-oflag SI temp-op1 temp-op2 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x0 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (and SI rn imm12)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x0 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (and SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x0 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (and SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 25 | 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-branch-link? | f-offset24 |
cond | 0x5 | 0x0 | offset24 |
(set pc offset24)
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0xe | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (and SI rn (inv UINT imm12))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xe | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (and SI rn (inv SI operand2))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xe | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (and SI rn (inv SI operand2))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 25 | 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-branch-link? | f-offset24 |
cond | 0x5 | 0x1 | offset24 |
(sequence () (set (reg SI h-gr 14) (and USI (add USI pc 4) -4)) (set pc offset24))
31 30 29 28 | 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 | 3 2 1 0 |
f-cond | f-op24 | f-bx-rn |
cond | 0x12fff1 | bx-rn |
(sequence () (set pc (and SI bx-rn 4294967294)) (if (and SI bx-rn 1) (set (reg BI h-tbit) 1)))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0xb | 0x1 | rn | rd | imm12 |
(sequence ((SI result)) (set result (addc SI rn imm12 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rn imm12 0)) (set vbit (add-oflag SI rn imm12 0)))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xb | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence ((SI result)) (set result (addc SI rn operand2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rn operand2 0)) (set vbit (add-oflag SI rn operand2 0)))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xb | 0x1 | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence ((SI result)) (set result (addc SI rn operand2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rn operand2 0)) (set vbit (add-oflag SI rn operand2 0)))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0xa | 0x1 | rn | rd | imm12 |
(sequence ((SI result)) (set result (subc SI rn imm12 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rn imm12 0))) (set vbit (sub-oflag SI rn imm12 0)))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xa | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence ((SI result)) (set result (subc SI rn operand2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rn operand2 0))) (set vbit (sub-oflag SI rn operand2 0)))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xa | 0x1 | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence ((SI result)) (set result (subc SI rn operand2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rn operand2 0))) (set vbit (sub-oflag SI rn operand2 0)))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x1 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (xor SI rn imm12)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x1 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (xor SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x1 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (xor SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (reg WI h-gr 14) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (reg WI h-gr 13) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (reg WI h-gr 12) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (reg WI h-gr 11) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (reg WI h-gr 10) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (reg WI h-gr 9) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (reg WI h-gr 8) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (sub SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (sub SI addr 4)) (set (reg SI h-cpsr) (reg SI h-spsr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (sub SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x1 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (sub SI addr 4)) (set (reg SI h-cpsr) (reg SI h-spsr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (sub SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x0 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (reg WI h-gr 14) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (reg WI h-gr 13) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (reg WI h-gr 12) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (reg WI h-gr 11) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (reg WI h-gr 10) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (reg WI h-gr 9) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (reg WI h-gr 8) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (sub SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set pc (mem WI addr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 14) (mem WI addr)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 13) (mem WI addr)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 12) (mem WI addr)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 11) (mem WI addr)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 10) (mem WI addr)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 9) (mem WI addr)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 8) (mem WI addr)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set pc (mem WI addr)) (set (reg SI h-cpsr) (reg SI h-spsr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set pc (mem WI addr)) (set (reg SI h-cpsr) (reg SI h-spsr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set pc (mem WI addr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 14) (mem WI addr)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 13) (mem WI addr)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 12) (mem WI addr)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 11) (mem WI addr)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 10) (mem WI addr)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 9) (mem WI addr)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 8) (mem WI addr)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (reg WI h-gr 8) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (reg WI h-gr 9) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (reg WI h-gr 10) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (reg WI h-gr 11) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (reg WI h-gr 12) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (reg WI h-gr 13) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (reg WI h-gr 14) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (add SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (add SI addr 4)) (set (reg SI h-cpsr) (reg SI h-spsr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (add SI addr 4)) (set (reg SI h-cpsr) (reg SI h-spsr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (reg WI h-gr 0) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (reg WI h-gr 1) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (reg WI h-gr 2) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (reg WI h-gr 3) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (reg WI h-gr 4) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (reg WI h-gr 5) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (reg WI h-gr 6) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (reg WI h-gr 7) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (reg WI h-gr 8) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (reg WI h-gr 9) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (reg WI h-gr 10) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (reg WI h-gr 11) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (reg WI h-gr 12) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (reg WI h-gr 13) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (reg WI h-gr 14) (mem WI addr)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set pc (mem WI addr)) (set addr (add SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 8) (mem WI addr)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 9) (mem WI addr)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 10) (mem WI addr)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 11) (mem WI addr)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 12) (mem WI addr)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 13) (mem WI addr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 14) (mem WI addr)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set pc (mem WI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set pc (mem WI addr)) (set (reg SI h-cpsr) (reg SI h-spsr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 8) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 8 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 9) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 9 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 10) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 10 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 11) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 11 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 12) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 12 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 13) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 13 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (reg WI h-gr 14) (mem WI addr)) (set (reg WI h-gr-usr (sub INT 14 8)) (mem WI addr))))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set pc (mem WI addr)) (set (reg SI h-cpsr) (reg SI h-spsr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 0) (mem WI addr)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 1) (mem WI addr)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 2) (mem WI addr)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 3) (mem WI addr)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 4) (mem WI addr)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 5) (mem WI addr)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 6) (mem WI addr)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 7) (mem WI addr)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 8) (mem WI addr)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 9) (mem WI addr)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 10) (mem WI addr)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 11) (mem WI addr)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 12) (mem WI addr)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 13) (mem WI addr)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (set (reg WI h-gr 14) (mem WI addr)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set pc (mem WI addr)))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (mem SI addr)) (set rd (mem SI addr))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem QI addr))) (set rd (zext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (zext SI (mem HI addr))) (set rd (zext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x0 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x0 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x0 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | 0x1 | 0x1 | 0x0 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x0 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | 0x1 | 0x1 | 0x0 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem QI addr))) (set rd (ext SI (mem QI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | rn | rd | 0x1 | 0x1 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | rn | rd | 0x1 | 0x1 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | rn | rd | 0x1 | 0x1 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | rn | rd | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (if (eq f-rd 15) (set pc (ext SI (mem HI addr))) (set rd (ext SI (mem HI addr)))) (set rn addr))
31 30 29 28 | 27 26 25 24 23 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-cond | f-op6 | f-acc? | f-set-cc? | f-mul-rd | f-mul-rn | f-rs | f-op-mul | f-rm |
cond | 0x0 | 0x1 | set-cc? | mul-rd | mul-rn | rs | 0x9 | rm |
(sequence ((WI result)) (set mul-rd (add SI (mul SI rm rs) mul-rn)) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0xd | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result imm12) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xd | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result operand2) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xd | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result operand2) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 20 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op5 | f-psr | f-op-mrs1 | f-rd | f-op-mrs2 |
cond | 0x2 | 0x0 | 0xf | rd | 0x0 |
(set rd (reg SI h-cpsr))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 20 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op5 | f-psr | f-op-mrs1 | f-rd | f-op-mrs2 |
cond | 0x2 | 0x1 | 0xf | rd | 0x0 |
(set rd (reg SI h-spsr))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 20 19 18 17 16 15 14 13 12 | 11 10 9 8 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-psr | f-op-msr1 | f-op-msr2 | f-rm |
cond | 0x2 | 0x0 | 0x29f | 0x0 | rm |
(set (reg SI h-cpsr) rm)
31 30 29 28 | 27 26 25 24 23 | 22 | 21 20 19 18 17 16 15 14 13 12 | 11 10 9 8 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-psr | f-op-msr1 | f-op-msr2 | f-rm |
cond | 0x2 | 0x1 | 0x29f | 0x0 | rm |
(set (reg SI h-spsr) rm)
31 30 29 28 | 27 26 25 24 23 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-cond | f-op6 | f-acc? | f-set-cc? | f-mul-rd | f-mul-rn | f-rs | f-op-mul | f-rm |
cond | 0x0 | 0x0 | set-cc? | mul-rd | mul-rn | rs | 0x9 | rm |
(sequence ((WI result)) (set result (mul SI rm rs)) (set mul-rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0xf | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (inv UINT imm12)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xf | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (inv SI operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xf | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (inv SI operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0xc | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (or SI rn imm12)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (set zbit (eq result 0)) (set nbit (lt result 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xc | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (or SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0xc | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (or SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x3 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (sub UINT imm12 rn)) (if (eq f-rd 15) (sequence () (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr))) (set pc result)) (sequence () (if set-cc? (sequence ((SI result)) (set result (subc UINT imm12 rn 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag UINT imm12 rn 0))) (set vbit (sub-oflag UINT imm12 rn 0)))) (set rd result))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x3 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set temp-op1 rn) (set temp-op2 operand2) (set result (sub SI operand2 rn)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op2 temp-op1 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op2 temp-op1 0))) (set vbit (sub-oflag SI temp-op2 temp-op1 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x3 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set temp-op1 rn) (set temp-op2 operand2) (set result (sub SI operand2 rn)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op2 temp-op1 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op2 temp-op1 0))) (set vbit (sub-oflag SI temp-op2 temp-op1 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x7 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (subc UINT imm12 rn (not BI cbit))) (if (eq f-rd 15) (sequence () (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr))) (set pc result)) (sequence () (if set-cc? (sequence ((SI result)) (set result (subc UINT imm12 rn (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag UINT imm12 rn (not BI cbit)))) (set vbit (sub-oflag UINT imm12 rn (not BI cbit))))) (set rd result))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x7 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set temp-op1 rn) (set temp-op2 operand2) (set result (subc SI operand2 rn (not BI cbit))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op2 temp-op1 (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op2 temp-op1 (not BI cbit)))) (set vbit (sub-oflag SI temp-op2 temp-op1 (not BI cbit))))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x7 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set temp-op1 rn) (set temp-op2 operand2) (set result (subc SI operand2 rn (not BI cbit))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op2 temp-op1 (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op2 temp-op1 (not BI cbit)))) (set vbit (sub-oflag SI temp-op2 temp-op1 (not BI cbit))))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x6 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (subc SI rn imm12 (not BI cbit))) (if (eq f-rd 15) (sequence () (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr))) (set pc result)) (sequence () (if set-cc? (sequence ((SI result)) (set result (subc SI rn imm12 (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rn imm12 (not BI cbit)))) (set vbit (sub-oflag SI rn imm12 (not BI cbit))))) (set rd result))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x6 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set temp-op1 rn) (set temp-op2 operand2) (set result (subc SI rn operand2 (not BI cbit))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op1 temp-op2 (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op1 temp-op2 (not BI cbit)))) (set vbit (sub-oflag SI temp-op1 temp-op2 (not BI cbit))))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x6 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set temp-op1 rn) (set temp-op2 operand2) (set result (subc SI rn operand2 (not BI cbit))) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op1 temp-op2 (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op1 temp-op2 (not BI cbit)))) (set vbit (sub-oflag SI temp-op1 temp-op2 (not BI cbit))))))))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-unsigned? | f-acc? | f-set-cc? | f-rdhi | f-rdlo | f-rs | f-op-mul | f-rm |
cond | 0x1 | 0x1 | 0x1 | set-cc? | rdhi | rdlo | rs | 0x9 | rm |
(sequence ((DI mul-result) (SI hi) (SI lo)) (set mul-result (join DI SI rdhi rdlo)) (set mul-result (add DI (mul DI (ext DI rs) (ext DI rm)) mul-result)) (set rdhi (subword SI mul-result 0)) (set rdlo (subword SI mul-result 1)) (if set-cc? (sequence () (set zbit (eq mul-result 0)) (set nbit (lt mul-result 0)))))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-unsigned? | f-acc? | f-set-cc? | f-rdhi | f-rdlo | f-rs | f-op-mul | f-rm |
cond | 0x1 | 0x1 | 0x0 | set-cc? | rdhi | rdlo | rs | 0x9 | rm |
(sequence ((DI mul-result) (SI hi) (SI lo)) (set mul-result (mul DI (ext DI rs) (ext DI rm))) (set rdhi (subword SI mul-result 0)) (set rdlo (subword SI mul-result 1)) (if set-cc? (sequence () (set zbit (eq mul-result 0)) (set nbit (lt mul-result 0)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (mem WI addr) (reg WI h-gr 14)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (mem WI addr) (reg WI h-gr 13)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (mem WI addr) (reg WI h-gr 12)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (mem WI addr) (reg WI h-gr 11)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (mem WI addr) (reg WI h-gr 10)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (mem WI addr) (reg WI h-gr 9)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (mem WI addr) (reg WI h-gr 8)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (sub SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (sub SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (sub SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (mem WI addr) (reg WI h-gr 14)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (mem WI addr) (reg WI h-gr 13)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (mem WI addr) (reg WI h-gr 12)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (mem WI addr) (reg WI h-gr 11)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (mem WI addr) (reg WI h-gr 10)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (mem WI addr) (reg WI h-gr 9)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (mem WI addr) (reg WI h-gr 8)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (sub SI addr 4)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (sub SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 14)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 13)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 12)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 11)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 10)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 9)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 8)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 14)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 13)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 12)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 11)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 10)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 9)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 8)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (sub SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (mem WI addr) (reg WI h-gr 8)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (mem WI addr) (reg WI h-gr 9)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (mem WI addr) (reg WI h-gr 10)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (mem WI addr) (reg WI h-gr 11)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (mem WI addr) (reg WI h-gr 12)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (mem WI addr) (reg WI h-gr 13)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (mem WI addr) (reg WI h-gr 14)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (add SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (add SI addr 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (add SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set (mem WI addr) (reg WI h-gr 0)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set (mem WI addr) (reg WI h-gr 1)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set (mem WI addr) (reg WI h-gr 2)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set (mem WI addr) (reg WI h-gr 3)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set (mem WI addr) (reg WI h-gr 4)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set (mem WI addr) (reg WI h-gr 5)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set (mem WI addr) (reg WI h-gr 6)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set (mem WI addr) (reg WI h-gr 7)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set (mem WI addr) (reg WI h-gr 8)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set (mem WI addr) (reg WI h-gr 9)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set (mem WI addr) (reg WI h-gr 10)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set (mem WI addr) (reg WI h-gr 11)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set (mem WI addr) (reg WI h-gr 12)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set (mem WI addr) (reg WI h-gr 13)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set (mem WI addr) (reg WI h-gr 14)) (set addr (add SI addr 4)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set (mem WI addr) (add WI (reg WI h-gr 15) 4)) (set addr (add SI addr 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 8)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 9)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 10)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 11)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 12)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 13)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 14)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 8)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 8 8)))))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 9)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 9 8)))))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 10)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 10 8)))))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 11)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 11 8)))))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 12)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 12 8)))))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 13)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 13 8)))))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (if (and UINT reglist (sll INT 1 15)) (set (mem WI addr) (reg WI h-gr 14)) (set (mem WI addr) (reg WI h-gr-usr (sub INT 14 8)))))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-load-psr? | f-write-back? | f-load? | f-rn | f-reg-list |
cond | 0x4 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | rn | reglist |
(sequence ((WI addr)) (set addr rn) (if (and UINT reglist (sll INT 1 0)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 0)))) (if (and UINT reglist (sll INT 1 1)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 1)))) (if (and UINT reglist (sll INT 1 2)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 2)))) (if (and UINT reglist (sll INT 1 3)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 3)))) (if (and UINT reglist (sll INT 1 4)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 4)))) (if (and UINT reglist (sll INT 1 5)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 5)))) (if (and UINT reglist (sll INT 1 6)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 6)))) (if (and UINT reglist (sll INT 1 7)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 7)))) (if (and UINT reglist (sll INT 1 8)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 8)))) (if (and UINT reglist (sll INT 1 9)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 9)))) (if (and UINT reglist (sll INT 1 10)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 10)))) (if (and UINT reglist (sll INT 1 11)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 11)))) (if (and UINT reglist (sll INT 1 12)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 12)))) (if (and UINT reglist (sll INT 1 13)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 13)))) (if (and UINT reglist (sll INT 1 14)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (reg WI h-gr 14)))) (if (and UINT reglist (sll INT 1 15)) (sequence () (set addr (add SI addr 4)) (set (mem WI addr) (add WI (reg WI h-gr 15) 4)))) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem SI addr) rd) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem SI addr) rd) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem SI addr) rd) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem SI addr) rd) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem SI addr) rd) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem SI addr) rd) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem SI addr) rd) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem SI addr) rd) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (set (mem SI addr) rd))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (set (mem SI addr) rd))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (set (mem SI addr) rd) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (set (mem SI addr) rd) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (set (mem SI addr) rd))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (set (mem SI addr) rd))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (set (mem SI addr) rd) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (set (mem SI addr) rd) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr rn) (set (mem QI addr) (trunc QI rd)) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (set (mem QI addr) (trunc QI rd)))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (set (mem QI addr) (trunc QI rd)))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (sub SI rn offset)) (set (mem QI addr) (trunc QI rd)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (sub SI rn offset)) (set (mem QI addr) (trunc QI rd)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (set (mem QI addr) (trunc QI rd)))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (set (mem QI addr) (trunc QI rd)))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-uimm12 |
cond | 0x1 | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | rn | rd | uimm12 |
(sequence ((SI addr) (SI offset)) (set offset uimm12) (set addr (add SI rn offset)) (set (mem QI addr) (trunc QI rd)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-preindex? | f-up-down | f-byte-qty? | f-write-back? | f-load? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI addr) (SI offset)) (set offset (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set addr (add SI rn offset)) (set (mem QI addr) (trunc QI rd)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (set (mem HI addr) (trunc HI rd)) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (set (mem HI addr) (trunc HI rd)) (set addr (sub SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr rn) (set (mem HI addr) (trunc HI rd)) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr rn) (set (mem HI addr) (trunc HI rd)) (set addr (add SI rn offset)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (set (mem HI addr) (trunc HI rd)))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (set (mem HI addr) (trunc HI rd)))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (sub SI rn offset)) (set (mem HI addr) (trunc HI rd)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (sub SI rn offset)) (set (mem HI addr) (trunc HI rd)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (set (mem HI addr) (trunc HI rd)))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (set (mem HI addr) (trunc HI rd)))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 | 8 | 7 6 5 4 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-hdt-offset8 |
cond | 0x0 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | rn | rd | 0x1 | 0x0 | 0x1 | 0x1 | hdt-offset8 |
(sequence ((SI addr) (SI offset)) (set offset hdt-offset8) (set addr (add SI rn offset)) (set (mem HI addr) (trunc HI rd)) (set rn addr))
31 30 29 28 | 27 26 25 | 24 | 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 | 5 | 4 | 3 2 1 0 |
f-cond | f-op3 | f-preindex? | f-up-down | f-bit22 | f-write-back? | f-load? | f-rn | f-rd | f-offset4-hi | f-bit7 | f-signed? | f-halfword? | f-bit4 | f-rm |
cond | 0x0 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | rn | rd | 0x0 | 0x1 | 0x0 | 0x1 | 0x1 | rm |
(sequence ((SI addr) (SI offset)) (set offset rm) (set addr (add SI rn offset)) (set (mem HI addr) (trunc HI rd)) (set rn addr))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-imm12 |
cond | 0x0 | 0x1 | 0x2 | set-cc? | rn | rd | imm12 |
(sequence ((SI result)) (set result (sub SI rn imm12)) (if (eq f-rd 15) (sequence () (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr))) (set pc result)) (sequence () (if set-cc? (sequence ((SI result)) (set result (subc SI rn imm12 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rn imm12 0))) (set vbit (sub-oflag SI rn imm12 0)))) (set rd result))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x2 | set-cc? | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set temp-op1 rn) (set temp-op2 operand2) (set result (sub SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op1 temp-op2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op1 temp-op2 0))) (set vbit (sub-oflag SI temp-op1 temp-op2 0)))))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x2 | set-cc? | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (SI result) (SI temp-op1) (SI temp-op2)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set temp-op1 rn) (set temp-op2 operand2) (set result (sub SI rn operand2)) (if (eq f-rd 15) (sequence () (set pc result) (if set-cc? (set (reg SI h-cpsr) (reg SI h-spsr)))) (sequence () (set rd result) (if set-cc? (sequence ((SI result)) (set result (subc SI temp-op1 temp-op2 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI temp-op1 temp-op2 0))) (set vbit (sub-oflag SI temp-op1 temp-op2 0)))))))
31 30 29 28 | 27 26 25 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op4 | f-swi-comment |
cond | 0xf | swi-comment |
(set pc (c-call SI "arm_swi" pc swi-comment))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-byte-qty? | f-op-swap1 | f-rn | f-rd | f-op-swap2 | f-rm |
cond | 0x2 | 0x0 | 0x0 | rn | rd | 0x9 | rm |
(sequence ((WI temp)) (set temp (mem WI rn)) (set (mem WI rn) rm) (set rd temp))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-byte-qty? | f-op-swap1 | f-rn | f-rd | f-op-swap2 | f-rm |
cond | 0x2 | 0x1 | 0x0 | rn | rd | 0x9 | rm |
(sequence ((WI temp)) (set temp (mem QI rn)) (set (mem QI rn) rm) (set rd temp))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-ror-imm8 |
cond | 0x0 | 0x1 | 0x9 | 0x1 | rn | rd | ror-imm8 |
(sequence ((BI carry-out)) (if (eq f-ror-imm8-rotate 0) (set carry-out cbit) (set carry-out (lt ror-imm8 0))) (sequence () (sequence () (set zbit (eq (xor SI rn ror-imm8) 0)) (set nbit (lt (xor SI rn ror-imm8) 0))) (set cbit carry-out)))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x9 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (xor SI rn operand2)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x9 | 0x1 | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (xor SI rn operand2)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-ror-imm8 |
cond | 0x0 | 0x1 | 0x8 | 0x1 | rn | rd | ror-imm8 |
(sequence ((BI carry-out)) (if (eq f-ror-imm8-rotate 0) (set carry-out cbit) (set carry-out (lt ror-imm8 0))) (sequence () (sequence () (set zbit (eq (and SI rn ror-imm8) 0)) (set nbit (lt (and SI rn ror-imm8) 0))) (set cbit carry-out)))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftimm | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x8 | 0x1 | rn | rd | operand2-shiftimm | operand2-shifttype | 0x0 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_immshift" rm operand2-shifttype operand2-shiftimm)) (set carry-out (c-call BI "compute_carry_out_immshift" rm operand2-shifttype operand2-shiftimm cbit)) (set result (and SI rn operand2)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))
31 30 29 28 | 27 26 | 25 | 24 23 22 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 | 6 5 | 4 | 3 2 1 0 |
f-cond | f-op2 | f-imm? | f-op-alu | f-set-cc? | f-rn | f-rd | f-operand2-shiftreg | f-bit7 | f-operand2-shifttype | f-operand2-reg? | f-rm |
cond | 0x0 | 0x0 | 0x8 | 0x1 | rn | rd | operand2-shiftreg | 0x0 | operand2-shifttype | 0x1 | rm |
(sequence ((SI operand2) (BI carry-out) (SI result)) (set operand2 (c-call SI "compute_operand2_regshift" rm operand2-shifttype operand2-shiftreg)) (set carry-out (c-call BI "compute_carry_out_regshift" rm operand2-shifttype operand2-shiftreg cbit)) (set result (and SI rn operand2)) (if (eq f-rd 15) (set (reg SI h-cpsr) (reg SI h-spsr)) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out))))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-unsigned? | f-acc? | f-set-cc? | f-rdhi | f-rdlo | f-rs | f-op-mul | f-rm |
cond | 0x1 | 0x0 | 0x1 | set-cc? | rdhi | rdlo | rs | 0x9 | rm |
(sequence ((DI mul-result) (SI hi) (SI lo)) (set mul-result (join DI SI rdhi rdlo)) (set mul-result (add DI (mul DI (zext DI rs) (zext DI rm)) mul-result)) (set rdhi (subword SI mul-result 0)) (set rdlo (subword SI mul-result 1)) (if set-cc? (sequence () (set zbit (eq mul-result 0)) (set nbit (lt mul-result 0)))))
31 30 29 28 | 27 26 25 24 23 | 22 | 21 | 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-cond | f-op5 | f-unsigned? | f-acc? | f-set-cc? | f-rdhi | f-rdlo | f-rs | f-op-mul | f-rm |
cond | 0x1 | 0x0 | 0x0 | set-cc? | rdhi | rdlo | rs | 0x9 | rm |
(sequence ((DI mul-result) (SI hi) (SI lo)) (set mul-result (mul DI (zext DI rs) (zext DI rm))) (set rdhi (subword SI mul-result 0)) (set rdlo (subword SI mul-result 1)) (if set-cc? (sequence () (set zbit (eq mul-result 0)) (set nbit (lt mul-result 0)))))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/