Instructions

• arm7tdmi - ARM 7TDMI core
• MEM - Memory
• ALU - ALU
• BR - Branch
• alphabetically

arm7tdmi MEM - Memory

• stmda - Store multiple registers (postindex, decrement)
• stmda-sw - Store multiple registers (postindex, decrement, switch)
• stmda-sw-wb - Store multiple registers (postindex, decrement, switch, writeback)
• stmda-wb - Store multiple registers (postindex, decrement, writeback)
• stmdb - Store multiple registers (preindex, decrement)
• stmdb-sw - Store multiple registers (preindex, decrement, switch)
• stmdb-sw-wb - Store multiple registers (preindex, decrement, switch, writeback)
• stmdb-wb - Store multiple registers (preindex, decrement, writeback)
• stmia - Store multiple registers (postindex, increment)
• stmia-sw - Store multiple registers (postindex, increment, switch)
• stmia-sw-wb - Store multiple registers (postindex, increment, switch, writeback)
• stmia-wb - Store multiple registers (postindex, increment, writeback)
• stmib - Store multiple registers (preindex, increment)
• stmib-sw - Store multiple registers (preindex, increment, switch)
• stmib-sw-wb - Store multiple registers (preindex, increment, switch, writeback)
• stmib-wb - Store multiple registers (preindex, increment, writeback)
• str-post-dec-imm-offset - Store word (postindex, decrement), immediate offset
• str-post-dec-nonpriv-imm-offset - Store word (postindex, decrement, nonpriv), immediate offset
• str-post-dec-nonpriv-reg-offset - Store word (postindex, decrement, nonpriv), register offset
• str-post-dec-reg-offset - Store word (postindex, decrement), register offset
• str-post-inc-imm-offset - Store word (postindex, increment), immediate offset
• str-post-inc-nonpriv-imm-offset - Store word (postindex, increment, nonpriv), immediate offset
• str-post-inc-nonpriv-reg-offset - Store word (postindex, increment, nonpriv), register offset
• str-post-inc-reg-offset - Store word (postindex, increment), register offset
• str-pre-dec-imm-offset - Store word (preindex, decrement), immediate offset
• str-pre-dec-reg-offset - Store word (preindex, decrement), register offset
• str-pre-dec-wb-imm-offset - Store word (preindex, decrement, writeback), immediate offset
• str-pre-dec-wb-reg-offset - Store word (preindex, decrement, writeback), register offset
• str-pre-inc-imm-offset - Store word (preindex, increment), immediate offset
• str-pre-inc-reg-offset - Store word (preindex, increment), register offset
• str-pre-inc-wb-imm-offset - Store word (preindex, increment, writeback), immediate offset
• str-pre-inc-wb-reg-offset - Store word (preindex, increment, writeback), register offset
• strb-post-dec-imm-offset - Store byte (postindex, decrement), immediate offset
• strb-post-dec-nonpriv-imm-offset - Store byte (postindex, decrement, nonpriv), immediate offset
• strb-post-dec-nonpriv-reg-offset - Store byte (postindex, decrement, nonpriv), register offset
• strb-post-dec-reg-offset - Store byte (postindex, decrement), register offset
• strb-post-inc-imm-offset - Store byte (postindex, increment), immediate offset
• strb-post-inc-nonpriv-imm-offset - Store byte (postindex, increment, nonpriv), immediate offset
• strb-post-inc-nonpriv-reg-offset - Store byte (postindex, increment, nonpriv), register offset
• strb-post-inc-reg-offset - Store byte (postindex, increment), register offset
• strb-pre-dec-imm-offset - Store byte (preindex, decrement), immediate offset
• strb-pre-dec-reg-offset - Store byte (preindex, decrement), register offset
• strb-pre-dec-wb-imm-offset - Store byte (preindex, decrement, writeback), immediate offset
• strb-pre-dec-wb-reg-offset - Store byte (preindex, decrement, writeback), register offset
• strb-pre-inc-imm-offset - Store byte (preindex, increment), immediate offset
• strb-pre-inc-reg-offset - Store byte (preindex, increment), register offset
• strb-pre-inc-wb-imm-offset - Store byte (preindex, increment, writeback), immediate offset
• strb-pre-inc-wb-reg-offset - Store byte (preindex, increment, writeback), register offset
• strh-post-dec-imm-offset - Store halfword (postdecrement), immediate offset
• strh-post-dec-reg-offset - Store halfword (postdecrement), register offset
• strh-post-inc-imm-offset - Store halfword (postindex, increment), immediate offset
• strh-post-inc-reg-offset - Store halfword (postindex, increment), register offset
• strh-pre-dec-imm-offset - Store halfword (predecrement), immediate offset
• strh-pre-dec-reg-offset - Store halfword (predecrement), register offset
• strh-pre-dec-wb-imm-offset - Store halfword (predec, writeback), immediate offset
• strh-pre-dec-wb-reg-offset - Store halfword (predec, writeback), register offset
• strh-pre-inc-imm-offset - Store halfword (preincrement), immediate offset
• strh-pre-inc-reg-offset - Store halfword (preincrement), register offset
• strh-pre-inc-wb-imm-offset - Store halfword (preinc, writeback), immediate offset
• strh-pre-inc-wb-reg-offset - Store halfword (preinc, writeback), register offset
• swp - Swap word
• swpb - Swap byte

arm7tdmi ALU - ALU

• cmn-imm - Compare negative immediate
• cmn-reg/imm-shift - Compare negative immediate shift
• cmn-reg/reg-shift - Compare negative register shift
• cmp-imm - Compare immediate
• cmp-reg/imm-shift - Compare immediate shift
• cmp-reg/reg-shift - Compare register shift
• mla - Multiply and accumulate
• mrs-c - Transfer CPSR contents to a register
• mrs-s - Transfer SPSR contents to a register
• msr-c - Transfer register contents to CPSR
• msr-s - Transfer register contents to SPSR
• mul - Multiply
• smlal - Multiply long and accumulate (signed)
• smull - Multiply long (signed)
• teq-imm - Test equal immediate
• teq-reg/imm-shift - Test equal immediate shift
• teq-reg/reg-shift - Test equal register shift
• tst-imm - Test immediate
• tst-reg/imm-shift - Test immediate shift
• tst-reg/reg-shift - Test register shift
• umlal - Multiply long and accumulate (unsigned)
• umull - Multiply long (unsigned)

arm7tdmi BR - Branch

• adc-imm - Add with carry immediate
• adc-reg/imm-shift - Add with carry immediate shift
• adc-reg/reg-shift - Add with carry register shift
• add-imm - Add immediate
• add-reg/imm-shift - Add immediate shift
• add-reg/reg-shift - Add register shift
• and-imm - Bitwise AND immediate
• and-reg/imm-shift - Bitwise AND immediate shift
• and-reg/reg-shift - Bitwise AND register shift
• b - Branch
• bic-imm - Bit clear immediate
• bic-reg/imm-shift - Bit clear immediate shift
• bic-reg/reg-shift - Bit clear register shift
• bl - Branch and link
• bx - Branch and exchange
• eor-imm - Exclusive OR immediate
• eor-reg/imm-shift - Exclusive OR immediate shift
• eor-reg/reg-shift - Exclusive OR register shift
• ldmda - Load multiple registers (postindex, decrement)
• ldmda-sw - Load multiple registers (postindex, decrement, switch)
• ldmda-sw-wb - Load multiple registers (postindex, decrement, switch, writeback)
• ldmda-wb - Load multiple registers (postindex, decrement, writeback)
• ldmdb - Load multiple registers (preindex, decrement)
• ldmdb-sw - Load multiple registers (preindex, decrement, switch)
• ldmdb-sw-wb - Load multiple registers (preindex, decrement, switch, writeback)
• ldmdb-wb - Load multiple registers (preindex, decrement, writeback)
• ldmia - Load multiple registers (postindex, increment)
• ldmia-sw - Load multiple registers (postindex, increment, switch)
• ldmia-sw-wb - Load multiple registers (postindex, increment, switch, writeback)
• ldmia-wb - Load multiple registers (postindex, increment, writeback)
• ldmib - Load multiple register (preindex, increment)
• ldmib-sw - Load multiple register (preindex, increment, switch)
• ldmib-sw-wb - Load multiple registers (preindex, increment, switch, writeback)
• ldmib-wb - Load multiple registers (preindex, increment, writeback)
• ldr-post-dec-imm-offset - Load word (postindex, decrement), immediate offset
• ldr-post-dec-nonpriv-imm-offset - Load word (postindex, decrement, nonpriv), immediate offset
• ldr-post-dec-nonpriv-reg-offset - Load word (postindex, decrement, nonpriv), register offset
• ldr-post-dec-reg-offset - Load word (postindex, decrement), register offset
• ldr-post-inc-imm-offset - Load word (postindex, increment), immediate offset
• ldr-post-inc-nonpriv-imm-offset - Load word (postindex, increment, nonpriv), immediate offset
• ldr-post-inc-nonpriv-reg-offset - Load word (postindex, increment, nonpriv), register offset
• ldr-post-inc-reg-offset - Load word (postindex, increment), register offset
• ldr-pre-dec-imm-offset - Load word (preindex, decrement), immediate offset
• ldr-pre-dec-reg-offset - Load word (preindex, decrement), register offset
• ldr-pre-dec-wb-imm-offset - Load word (preindex, decrement, writeback), immediate offset
• ldr-pre-dec-wb-reg-offset - Load word (preindex, decrement, writeback), register offset
• ldr-pre-inc-imm-offset - Load word (preindex, increment), immediate offset
• ldr-pre-inc-reg-offset - Load word (preindex, increment), register offset
• ldr-pre-inc-wb-imm-offset - Load word (preindex, increment, writeback), immediate offset
• ldr-pre-inc-wb-reg-offset - Load word (preindex, increment, writeback), register offset
• ldrb-post-dec-imm-offset - Load byte (postindex, decrement), immediate offset
• ldrb-post-dec-nonpriv-imm-offset - Load byte (postindex, decrement, nonpriv), immediate offset
• ldrb-post-dec-nonpriv-reg-offset - Load byte (postindex, decrement, nonpriv), register offset
• ldrb-post-dec-reg-offset - Load byte (postindex, decrement), register offset
• ldrb-post-inc-imm-offset - Load byte (postindex, increment), immediate offset
• ldrb-post-inc-nonpriv-imm-offset - Load byte (postindex, increment, nonpriv), immediate offset
• ldrb-post-inc-nonpriv-reg-offset - Load byte (postindex, increment, nonpriv), register offset
• ldrb-post-inc-reg-offset - Load byte (postindex, increment), register offset
• ldrb-pre-dec-imm-offset - Load byte (preindex, decrement), immediate offset
• ldrb-pre-dec-reg-offset - Load byte (preindex, decrement), register offset
• ldrb-pre-dec-wb-imm-offset - Load byte (preindex, decrement, writeback), immediate offset
• ldrb-pre-dec-wb-reg-offset - Load byte (preindex, decrement, writeback), register offset
• ldrb-pre-inc-imm-offset - Load byte (preindex, increment), immediate offset
• ldrb-pre-inc-reg-offset - Load byte (preindex, increment), register offset
• ldrb-pre-inc-wb-imm-offset - Load byte (preindex, increment, writeback), immediate offset
• ldrb-pre-inc-wb-reg-offset - Load byte (preindex, increment, writeback), register offset
• ldrh-post-dec-imm-offset - Load halfword (postdecrement), immediate offset
• ldrh-post-dec-reg-offset - Load halfword (postdecrement), register offset
• ldrh-post-inc-imm-offset - Load halfword (postincrement), immediate offset
• ldrh-post-inc-reg-offset - Load halfword (postincrement), register offset
• ldrh-pre-dec-imm-offset - Load halfword (predecrement), immediate offset
• ldrh-pre-dec-reg-offset - Load halfword (predecrement), register offset
• ldrh-pre-dec-wb-imm-offset - Load halfword (predec, writeback), immediate offset
• ldrh-pre-dec-wb-reg-offset - Load halfword (predec, writeback), register offset
• ldrh-pre-inc-imm-offset - Load halfword (preincrement), immediate offset
• ldrh-pre-inc-reg-offset - Load halfword (preincrement), register offset
• ldrh-pre-inc-wb-imm-offset - Load halfword (preinc, writeback), immediate offset
• ldrh-pre-inc-wb-reg-offset - Load halfword (preinc, writeback), register offset
• ldrsb-post-dec-imm-offset - Load signed byte (postdecrement), immediate offset
• ldrsb-post-dec-reg-offset - Load signed byte (postdecrement), register offset
• ldrsb-post-inc-imm-offset - Load signed byte (postindex, increment), immediate offset
• ldrsb-post-inc-reg-offset - Load signed byte (postindex, increment), register offset
• ldrsb-pre-dec-imm-offset - Load signed byte (predecrement), immediate offset
• ldrsb-pre-dec-reg-offset - Load signed byte (predecrement), register offset
• ldrsb-pre-dec-wb-imm-offset - Load signed byte (predec, writeback), immediate offset
• ldrsb-pre-dec-wb-reg-offset - Load signed byte (predec, writeback), register offset
• ldrsb-pre-inc-imm-offset - Load signed byte (preincrement), immediate offset
• ldrsb-pre-inc-reg-offset - Load signed byte (preincrement), register offset
• ldrsb-pre-inc-wb-imm-offset - Load signed byte (preinc, writeback), immediate offset
• ldrsb-pre-inc-wb-reg-offset - Load signed byte (preinc, writeback), register offset
• ldrsh-post-dec-imm-offset - Load signed halfword (postdecrement), immediate offset
• ldrsh-post-dec-reg-offset - Load signed halfword (postdecrement), register offset
• ldrsh-post-inc-imm-offset - Load signed halfword (postincrement), immediate offset
• ldrsh-post-inc-reg-offset - Load signed halfword (postincrement), register offset
• ldrsh-pre-dec-imm-offset - Load signed halfword (predecrement), immediate offset
• ldrsh-pre-dec-reg-offset - Load signed halfword (predecrement), register offset
• ldrsh-pre-dec-wb-imm-offset - Load signed halfword (predec, writeback), immediate offset
• ldrsh-pre-dec-wb-reg-offset - Load signed halfword (predec, writeback), register offset
• ldrsh-pre-inc-imm-offset - Load signed halfword (preincrement), immediate offset
• ldrsh-pre-inc-reg-offset - Load signed halfword (preincrement), register offset
• ldrsh-pre-inc-wb-imm-offset - Load signed halfword (preinc, writeback), immediate offset
• ldrsh-pre-inc-wb-reg-offset - Load signed halfword (preinc, writeback), register offset
• mov-imm - Move immediate
• mov-reg/imm-shift - Move immediate shift
• mov-reg/reg-shift - Move register shift
• mvn-imm - Move (logical) negate immediate
• mvn-reg/imm-shift - Move negate immediate shift
• mvn-reg/reg-shift - Move negate register shift
• orr-imm - Bitwise OR immediate
• orr-reg/imm-shift - Bitwise OR immediate shift
• orr-reg/reg-shift - Bitwise OR register shift
• rsb-imm - Reverse subtract immediate
• rsb-reg/imm-shift - Reverse subtract immediate shift
• rsb-reg/reg-shift - Reverse subtract register shift
• rsc-imm - Reverse subtract with carry immediate
• rsc-reg/imm-shift - Reverse subtract with carry immediate shift
• rsc-reg/reg-shift - Reverse subtract with carry register shift
• sbc-imm - Subtract with carry immediate
• sbc-reg/imm-shift - Subtract with carry immediate shift
• sbc-reg/reg-shift - Subtract with carry register shift
• sub-imm - Subtract immediate
• sub-reg/imm-shift - Subtract immediate shift
• sub-reg/reg-shift - Subtract register shift
• swi - Software interrupt

arm7tdmi arm7tdmi - ARM 7TDMI core

• adc-imm - Add with carry immediate
• adc-reg/imm-shift - Add with carry immediate shift
• adc-reg/reg-shift - Add with carry register shift
• add-imm - Add immediate
• add-reg/imm-shift - Add immediate shift
• add-reg/reg-shift - Add register shift
• and-imm - Bitwise AND immediate
• and-reg/imm-shift - Bitwise AND immediate shift
• and-reg/reg-shift - Bitwise AND register shift
• b - Branch
• bic-imm - Bit clear immediate
• bic-reg/imm-shift - Bit clear immediate shift
• bic-reg/reg-shift - Bit clear register shift
• bl - Branch and link
• bx - Branch and exchange
• cmn-imm - Compare negative immediate
• cmn-reg/imm-shift - Compare negative immediate shift
• cmn-reg/reg-shift - Compare negative register shift
• cmp-imm - Compare immediate
• cmp-reg/imm-shift - Compare immediate shift
• cmp-reg/reg-shift - Compare register shift
• eor-imm - Exclusive OR immediate
• eor-reg/imm-shift - Exclusive OR immediate shift
• eor-reg/reg-shift - Exclusive OR register shift
• ldmda - Load multiple registers (postindex, decrement)
• ldmda-sw - Load multiple registers (postindex, decrement, switch)
• ldmda-sw-wb - Load multiple registers (postindex, decrement, switch, writeback)
• ldmda-wb - Load multiple registers (postindex, decrement, writeback)
• ldmdb - Load multiple registers (preindex, decrement)
• ldmdb-sw - Load multiple registers (preindex, decrement, switch)
• ldmdb-sw-wb - Load multiple registers (preindex, decrement, switch, writeback)
• ldmdb-wb - Load multiple registers (preindex, decrement, writeback)
• ldmia - Load multiple registers (postindex, increment)
• ldmia-sw - Load multiple registers (postindex, increment, switch)
• ldmia-sw-wb - Load multiple registers (postindex, increment, switch, writeback)
• ldmia-wb - Load multiple registers (postindex, increment, writeback)
• ldmib - Load multiple register (preindex, increment)
• ldmib-sw - Load multiple register (preindex, increment, switch)
• ldmib-sw-wb - Load multiple registers (preindex, increment, switch, writeback)
• ldmib-wb - Load multiple registers (preindex, increment, writeback)
• ldr-post-dec-imm-offset - Load word (postindex, decrement), immediate offset
• ldr-post-dec-nonpriv-imm-offset - Load word (postindex, decrement, nonpriv), immediate offset
• ldr-post-dec-nonpriv-reg-offset - Load word (postindex, decrement, nonpriv), register offset
• ldr-post-dec-reg-offset - Load word (postindex, decrement), register offset
• ldr-post-inc-imm-offset - Load word (postindex, increment), immediate offset
• ldr-post-inc-nonpriv-imm-offset - Load word (postindex, increment, nonpriv), immediate offset
• ldr-post-inc-nonpriv-reg-offset - Load word (postindex, increment, nonpriv), register offset
• ldr-post-inc-reg-offset - Load word (postindex, increment), register offset
• ldr-pre-dec-imm-offset - Load word (preindex, decrement), immediate offset
• ldr-pre-dec-reg-offset - Load word (preindex, decrement), register offset
• ldr-pre-dec-wb-imm-offset - Load word (preindex, decrement, writeback), immediate offset
• ldr-pre-dec-wb-reg-offset - Load word (preindex, decrement, writeback), register offset
• ldr-pre-inc-imm-offset - Load word (preindex, increment), immediate offset
• ldr-pre-inc-reg-offset - Load word (preindex, increment), register offset
• ldr-pre-inc-wb-imm-offset - Load word (preindex, increment, writeback), immediate offset
• ldr-pre-inc-wb-reg-offset - Load word (preindex, increment, writeback), register offset
• ldrb-post-dec-imm-offset - Load byte (postindex, decrement), immediate offset
• ldrb-post-dec-nonpriv-imm-offset - Load byte (postindex, decrement, nonpriv), immediate offset
• ldrb-post-dec-nonpriv-reg-offset - Load byte (postindex, decrement, nonpriv), register offset
• ldrb-post-dec-reg-offset - Load byte (postindex, decrement), register offset
• ldrb-post-inc-imm-offset - Load byte (postindex, increment), immediate offset
• ldrb-post-inc-nonpriv-imm-offset - Load byte (postindex, increment, nonpriv), immediate offset
• ldrb-post-inc-nonpriv-reg-offset - Load byte (postindex, increment, nonpriv), register offset
• ldrb-post-inc-reg-offset - Load byte (postindex, increment), register offset
• ldrb-pre-dec-imm-offset - Load byte (preindex, decrement), immediate offset
• ldrb-pre-dec-reg-offset - Load byte (preindex, decrement), register offset
• ldrb-pre-dec-wb-imm-offset - Load byte (preindex, decrement, writeback), immediate offset
• ldrb-pre-dec-wb-reg-offset - Load byte (preindex, decrement, writeback), register offset
• ldrb-pre-inc-imm-offset - Load byte (preindex, increment), immediate offset
• ldrb-pre-inc-reg-offset - Load byte (preindex, increment), register offset
• ldrb-pre-inc-wb-imm-offset - Load byte (preindex, increment, writeback), immediate offset
• ldrb-pre-inc-wb-reg-offset - Load byte (preindex, increment, writeback), register offset
• ldrh-post-dec-imm-offset - Load halfword (postdecrement), immediate offset
• ldrh-post-dec-reg-offset - Load halfword (postdecrement), register offset
• ldrh-post-inc-imm-offset - Load halfword (postincrement), immediate offset
• ldrh-post-inc-reg-offset - Load halfword (postincrement), register offset
• ldrh-pre-dec-imm-offset - Load halfword (predecrement), immediate offset
• ldrh-pre-dec-reg-offset - Load halfword (predecrement), register offset
• ldrh-pre-dec-wb-imm-offset - Load halfword (predec, writeback), immediate offset
• ldrh-pre-dec-wb-reg-offset - Load halfword (predec, writeback), register offset
• ldrh-pre-inc-imm-offset - Load halfword (preincrement), immediate offset
• ldrh-pre-inc-reg-offset - Load halfword (preincrement), register offset
• ldrh-pre-inc-wb-imm-offset - Load halfword (preinc, writeback), immediate offset
• ldrh-pre-inc-wb-reg-offset - Load halfword (preinc, writeback), register offset
• ldrsb-post-dec-imm-offset - Load signed byte (postdecrement), immediate offset
• ldrsb-post-dec-reg-offset - Load signed byte (postdecrement), register offset
• ldrsb-post-inc-imm-offset - Load signed byte (postindex, increment), immediate offset
• ldrsb-post-inc-reg-offset - Load signed byte (postindex, increment), register offset
• ldrsb-pre-dec-imm-offset - Load signed byte (predecrement), immediate offset
• ldrsb-pre-dec-reg-offset - Load signed byte (predecrement), register offset
• ldrsb-pre-dec-wb-imm-offset - Load signed byte (predec, writeback), immediate offset
• ldrsb-pre-dec-wb-reg-offset - Load signed byte (predec, writeback), register offset
• ldrsb-pre-inc-imm-offset - Load signed byte (preincrement), immediate offset
• ldrsb-pre-inc-reg-offset - Load signed byte (preincrement), register offset
• ldrsb-pre-inc-wb-imm-offset - Load signed byte (preinc, writeback), immediate offset
• ldrsb-pre-inc-wb-reg-offset - Load signed byte (preinc, writeback), register offset
• ldrsh-post-dec-imm-offset - Load signed halfword (postdecrement), immediate offset
• ldrsh-post-dec-reg-offset - Load signed halfword (postdecrement), register offset
• ldrsh-post-inc-imm-offset - Load signed halfword (postincrement), immediate offset
• ldrsh-post-inc-reg-offset - Load signed halfword (postincrement), register offset
• ldrsh-pre-dec-imm-offset - Load signed halfword (predecrement), immediate offset
• ldrsh-pre-dec-reg-offset - Load signed halfword (predecrement), register offset
• ldrsh-pre-dec-wb-imm-offset - Load signed halfword (predec, writeback), immediate offset
• ldrsh-pre-dec-wb-reg-offset - Load signed halfword (predec, writeback), register offset
• ldrsh-pre-inc-imm-offset - Load signed halfword (preincrement), immediate offset
• ldrsh-pre-inc-reg-offset - Load signed halfword (preincrement), register offset
• ldrsh-pre-inc-wb-imm-offset - Load signed halfword (preinc, writeback), immediate offset
• ldrsh-pre-inc-wb-reg-offset - Load signed halfword (preinc, writeback), register offset
• mla - Multiply and accumulate
• mov-imm - Move immediate
• mov-reg/imm-shift - Move immediate shift
• mov-reg/reg-shift - Move register shift
• mrs-c - Transfer CPSR contents to a register
• mrs-s - Transfer SPSR contents to a register
• msr-c - Transfer register contents to CPSR
• msr-s - Transfer register contents to SPSR
• mul - Multiply
• mvn-imm - Move (logical) negate immediate
• mvn-reg/imm-shift - Move negate immediate shift
• mvn-reg/reg-shift - Move negate register shift
• orr-imm - Bitwise OR immediate
• orr-reg/imm-shift - Bitwise OR immediate shift
• orr-reg/reg-shift - Bitwise OR register shift
• rsb-imm - Reverse subtract immediate
• rsb-reg/imm-shift - Reverse subtract immediate shift
• rsb-reg/reg-shift - Reverse subtract register shift
• rsc-imm - Reverse subtract with carry immediate
• rsc-reg/imm-shift - Reverse subtract with carry immediate shift
• rsc-reg/reg-shift - Reverse subtract with carry register shift
• sbc-imm - Subtract with carry immediate
• sbc-reg/imm-shift - Subtract with carry immediate shift
• sbc-reg/reg-shift - Subtract with carry register shift
• smlal - Multiply long and accumulate (signed)
• smull - Multiply long (signed)
• stmda - Store multiple registers (postindex, decrement)
• stmda-sw - Store multiple registers (postindex, decrement, switch)
• stmda-sw-wb - Store multiple registers (postindex, decrement, switch, writeback)
• stmda-wb - Store multiple registers (postindex, decrement, writeback)
• stmdb - Store multiple registers (preindex, decrement)
• stmdb-sw - Store multiple registers (preindex, decrement, switch)
• stmdb-sw-wb - Store multiple registers (preindex, decrement, switch, writeback)
• stmdb-wb - Store multiple registers (preindex, decrement, writeback)
• stmia - Store multiple registers (postindex, increment)
• stmia-sw - Store multiple registers (postindex, increment, switch)
• stmia-sw-wb - Store multiple registers (postindex, increment, switch, writeback)
• stmia-wb - Store multiple registers (postindex, increment, writeback)
• stmib - Store multiple registers (preindex, increment)
• stmib-sw - Store multiple registers (preindex, increment, switch)
• stmib-sw-wb - Store multiple registers (preindex, increment, switch, writeback)
• stmib-wb - Store multiple registers (preindex, increment, writeback)
• str-post-dec-imm-offset - Store word (postindex, decrement), immediate offset
• str-post-dec-nonpriv-imm-offset - Store word (postindex, decrement, nonpriv), immediate offset
• str-post-dec-nonpriv-reg-offset - Store word (postindex, decrement, nonpriv), register offset
• str-post-dec-reg-offset - Store word (postindex, decrement), register offset
• str-post-inc-imm-offset - Store word (postindex, increment), immediate offset
• str-post-inc-nonpriv-imm-offset - Store word (postindex, increment, nonpriv), immediate offset
• str-post-inc-nonpriv-reg-offset - Store word (postindex, increment, nonpriv), register offset
• str-post-inc-reg-offset - Store word (postindex, increment), register offset
• str-pre-dec-imm-offset - Store word (preindex, decrement), immediate offset
• str-pre-dec-reg-offset - Store word (preindex, decrement), register offset
• str-pre-dec-wb-imm-offset - Store word (preindex, decrement, writeback), immediate offset
• str-pre-dec-wb-reg-offset - Store word (preindex, decrement, writeback), register offset
• str-pre-inc-imm-offset - Store word (preindex, increment), immediate offset
• str-pre-inc-reg-offset - Store word (preindex, increment), register offset
• str-pre-inc-wb-imm-offset - Store word (preindex, increment, writeback), immediate offset
• str-pre-inc-wb-reg-offset - Store word (preindex, increment, writeback), register offset
• strb-post-dec-imm-offset - Store byte (postindex, decrement), immediate offset
• strb-post-dec-nonpriv-imm-offset - Store byte (postindex, decrement, nonpriv), immediate offset
• strb-post-dec-nonpriv-reg-offset - Store byte (postindex, decrement, nonpriv), register offset
• strb-post-dec-reg-offset - Store byte (postindex, decrement), register offset
• strb-post-inc-imm-offset - Store byte (postindex, increment), immediate offset
• strb-post-inc-nonpriv-imm-offset - Store byte (postindex, increment, nonpriv), immediate offset
• strb-post-inc-nonpriv-reg-offset - Store byte (postindex, increment, nonpriv), register offset
• strb-post-inc-reg-offset - Store byte (postindex, increment), register offset
• strb-pre-dec-imm-offset - Store byte (preindex, decrement), immediate offset
• strb-pre-dec-reg-offset - Store byte (preindex, decrement), register offset
• strb-pre-dec-wb-imm-offset - Store byte (preindex, decrement, writeback), immediate offset
• strb-pre-dec-wb-reg-offset - Store byte (preindex, decrement, writeback), register offset
• strb-pre-inc-imm-offset - Store byte (preindex, increment), immediate offset
• strb-pre-inc-reg-offset - Store byte (preindex, increment), register offset
• strb-pre-inc-wb-imm-offset - Store byte (preindex, increment, writeback), immediate offset
• strb-pre-inc-wb-reg-offset - Store byte (preindex, increment, writeback), register offset
• strh-post-dec-imm-offset - Store halfword (postdecrement), immediate offset
• strh-post-dec-reg-offset - Store halfword (postdecrement), register offset
• strh-post-inc-imm-offset - Store halfword (postindex, increment), immediate offset
• strh-post-inc-reg-offset - Store halfword (postindex, increment), register offset
• strh-pre-dec-imm-offset - Store halfword (predecrement), immediate offset
• strh-pre-dec-reg-offset - Store halfword (predecrement), register offset
• strh-pre-dec-wb-imm-offset - Store halfword (predec, writeback), immediate offset
• strh-pre-dec-wb-reg-offset - Store halfword (predec, writeback), register offset
• strh-pre-inc-imm-offset - Store halfword (preincrement), immediate offset
• strh-pre-inc-reg-offset - Store halfword (preincrement), register offset
• strh-pre-inc-wb-imm-offset - Store halfword (preinc, writeback), immediate offset
• strh-pre-inc-wb-reg-offset - Store halfword (preinc, writeback), register offset
• sub-imm - Subtract immediate
• sub-reg/imm-shift - Subtract immediate shift
• sub-reg/reg-shift - Subtract register shift
• swi - Software interrupt
• swp - Swap word
• swpb - Swap byte
• teq-imm - Test equal immediate
• teq-reg/imm-shift - Test equal immediate shift
• teq-reg/reg-shift - Test equal register shift
• tst-imm - Test immediate
• tst-reg/imm-shift - Test immediate shift
• tst-reg/reg-shift - Test register shift
• umlal - Multiply long and accumulate (unsigned)
• umull - Multiply long (unsigned)

Individual instructions descriptions

adc-imm - Add with carry immediate

• machines: base


• syntax: adc$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x5	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (addc SI rn imm12 cbit))
    (if (eq f-rd 15)
        (sequence
          ()
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr)))
          (set pc result))
        (sequence
          ()
          (if set-cc?
              (sequence
                ((SI result))
                (set result (addc SI rn imm12 cbit))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (add-cflag SI rn imm12 cbit))
                (set vbit (add-oflag SI rn imm12 cbit))))
          (set rd result))))
  

adc-reg/imm-shift - Add with carry immediate shift

• machines: base


• syntax: adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x5	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (addc SI rn operand2 cbit))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result (addc SI temp-op1 temp-op2 cbit))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (add-cflag SI temp-op1 temp-op2 cbit))
                (set vbit (add-oflag SI temp-op1 temp-op2 cbit)))))))
  

adc-reg/reg-shift - Add with carry register shift

• machines: base


• syntax: adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x5	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (addc SI rn operand2 cbit))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result (addc SI temp-op1 temp-op2 cbit))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (add-cflag SI temp-op1 temp-op2 cbit))
                (set vbit (add-oflag SI temp-op1 temp-op2 cbit)))))))
  

add-imm - Add immediate

• machines: base


• syntax: add$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x4	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (add SI rn imm12))
    (if (eq f-rd 15)
        (sequence
          ()
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr)))
          (set pc result))
        (sequence
          ()
          (if set-cc?
              (sequence
                ((SI result))
                (set result (addc SI rn imm12 0))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (add-cflag SI rn imm12 0))
                (set vbit (add-oflag SI rn imm12 0))))
          (set rd result))))
  

add-reg/imm-shift - Add immediate shift

• machines: base


• syntax: add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x4	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (add SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result (addc SI temp-op1 temp-op2 0))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (add-cflag SI temp-op1 temp-op2 0))
                (set vbit (add-oflag SI temp-op1 temp-op2 0)))))))
  

add-reg/reg-shift - Add register shift

• machines: base


• syntax: add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x4	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (add SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result (addc SI temp-op1 temp-op2 0))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (add-cflag SI temp-op1 temp-op2 0))
                (set vbit (add-oflag SI temp-op1 temp-op2 0)))))))
  

and-imm - Bitwise AND immediate

• machines: base


• syntax: and$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x0	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (and SI rn imm12))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (set zbit (eq result 0))
                (set nbit (lt result 0)))))))
  

and-reg/imm-shift - Bitwise AND immediate shift

• machines: base


• syntax: and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x0	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm
           cbit))
    (set result (and SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

and-reg/reg-shift - Bitwise AND register shift

• machines: base


• syntax: and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x0	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg
           cbit))
    (set result (and SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

b - Branch

• machines: base


• syntax: b$cond $offset24


• format:

  31 30 29 28	27 26 25	24	23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-branch-link?	f-offset24
  cond	0x5	0x0	offset24



• semantics:

  (set pc offset24)
  

bic-imm - Bit clear immediate

• machines: base


• syntax: bic$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0xe	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (and SI rn (inv UINT imm12)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (set zbit (eq result 0))
                (set nbit (lt result 0)))))))
  

bic-reg/imm-shift - Bit clear immediate shift

• machines: base


• syntax: bic$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xe	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm
           cbit))
    (set result (and SI rn (inv SI operand2)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

bic-reg/reg-shift - Bit clear register shift

• machines: base


• syntax: bic$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xe	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg
           cbit))
    (set result (and SI rn (inv SI operand2)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

bl - Branch and link

• machines: base


• syntax: bl$cond $offset24


• format:

  31 30 29 28	27 26 25	24	23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-branch-link?	f-offset24
  cond	0x5	0x1	offset24



• semantics:

  (sequence
    ()
    (set (reg SI h-gr 14)
         (and USI (add USI pc 4) -4))
    (set pc offset24))
  

bx - Branch and exchange

• machines: base


• syntax: bx$cond ${bx-rn}


• format:

  31 30 29 28	27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4	3 2 1 0
  f-cond	f-op24	f-bx-rn
  cond	0x12fff1	bx-rn



• semantics:

  (sequence
    ()
    (set pc (and SI bx-rn 4294967294))
    (if (and SI bx-rn 1) (set (reg BI h-tbit) 1)))
  

cmn-imm - Compare negative immediate

• machines: base


• syntax: cmn${cond}${set-cc?} $rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0xb	0x1	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (addc SI rn imm12 0))
    (sequence
      ()
      (set zbit (eq result 0))
      (set nbit (lt result 0)))
    (set cbit (add-cflag SI rn imm12 0))
    (set vbit (add-oflag SI rn imm12 0)))
  

cmn-reg/imm-shift - Compare negative immediate shift

• machines: base


• syntax: cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xb	0x1	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (if (eq f-rd 15)
        (set (reg SI h-cpsr) (reg SI h-spsr))
        (sequence
          ((SI result))
          (set result (addc SI rn operand2 0))
          (sequence
            ()
            (set zbit (eq result 0))
            (set nbit (lt result 0)))
          (set cbit (add-cflag SI rn operand2 0))
          (set vbit (add-oflag SI rn operand2 0)))))
  

cmn-reg/reg-shift - Compare negative register shift

• machines: base


• syntax: cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xb	0x1	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (if (eq f-rd 15)
        (set (reg SI h-cpsr) (reg SI h-spsr))
        (sequence
          ((SI result))
          (set result (addc SI rn operand2 0))
          (sequence
            ()
            (set zbit (eq result 0))
            (set nbit (lt result 0)))
          (set cbit (add-cflag SI rn operand2 0))
          (set vbit (add-oflag SI rn operand2 0)))))
  

cmp-imm - Compare immediate

• machines: base


• syntax: cmp${cond}${set-cc?} $rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0xa	0x1	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (subc SI rn imm12 0))
    (sequence
      ()
      (set zbit (eq result 0))
      (set nbit (lt result 0)))
    (set cbit (not BI (sub-cflag SI rn imm12 0)))
    (set vbit (sub-oflag SI rn imm12 0)))
  

cmp-reg/imm-shift - Compare immediate shift

• machines: base


• syntax: cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xa	0x1	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (if (eq f-rd 15)
        (set (reg SI h-cpsr) (reg SI h-spsr))
        (sequence
          ((SI result))
          (set result (subc SI rn operand2 0))
          (sequence
            ()
            (set zbit (eq result 0))
            (set nbit (lt result 0)))
          (set cbit (not BI (sub-cflag SI rn operand2 0)))
          (set vbit (sub-oflag SI rn operand2 0)))))
  

cmp-reg/reg-shift - Compare register shift

• machines: base


• syntax: cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xa	0x1	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (if (eq f-rd 15)
        (set (reg SI h-cpsr) (reg SI h-spsr))
        (sequence
          ((SI result))
          (set result (subc SI rn operand2 0))
          (sequence
            ()
            (set zbit (eq result 0))
            (set nbit (lt result 0)))
          (set cbit (not BI (sub-cflag SI rn operand2 0)))
          (set vbit (sub-oflag SI rn operand2 0)))))
  

eor-imm - Exclusive OR immediate

• machines: base


• syntax: eor$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x1	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (xor SI rn imm12))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (set zbit (eq result 0))
                (set nbit (lt result 0)))))))
  

eor-reg/imm-shift - Exclusive OR immediate shift

• machines: base


• syntax: eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x1	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm
           cbit))
    (set result (xor SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

eor-reg/reg-shift - Exclusive OR register shift

• machines: base


• syntax: eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x1	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg
           cbit))
    (set result (xor SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

ldmda - Load multiple registers (postindex, decrement)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x0	0x0	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set (reg WI h-gr 14) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set (reg WI h-gr 13) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set (reg WI h-gr 12) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set (reg WI h-gr 11) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set (reg WI h-gr 10) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set (reg WI h-gr 9) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set (reg WI h-gr 8) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (sub SI addr 4)))))
  

ldmda-sw - Load multiple registers (postindex, decrement, switch)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x0	0x1	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (sub SI addr 4))
          (set (reg SI h-cpsr) (reg SI h-spsr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (sub SI addr 4)))))
  

ldmda-sw-wb - Load multiple registers (postindex, decrement, switch, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x0	0x1	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (sub SI addr 4))
          (set (reg SI h-cpsr) (reg SI h-spsr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (sub SI addr 4))))
    (set rn addr))
  

ldmda-wb - Load multiple registers (postindex, decrement, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x0	0x0	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set (reg WI h-gr 14) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set (reg WI h-gr 13) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set (reg WI h-gr 12) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set (reg WI h-gr 11) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set (reg WI h-gr 10) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set (reg WI h-gr 9) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set (reg WI h-gr 8) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (sub SI addr 4))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (sub SI addr 4))))
    (set rn addr))
  

ldmdb - Load multiple registers (preindex, decrement)

• machines: base


• syntax: ldm$cond ..


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x0	0x0	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set pc (mem WI addr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 14) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 13) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 12) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 11) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 10) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 9) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 8) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr)))))
  

ldmdb-sw - Load multiple registers (preindex, decrement, switch)

• machines: base


• syntax: ldm$cond ..


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x0	0x1	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set pc (mem WI addr))
          (set (reg SI h-cpsr) (reg SI h-spsr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr)))))
  

ldmdb-sw-wb - Load multiple registers (preindex, decrement, switch, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x0	0x1	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set pc (mem WI addr))
          (set (reg SI h-cpsr) (reg SI h-spsr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr))))
    (set rn addr))
  

ldmdb-wb - Load multiple registers (preindex, decrement, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x0	0x0	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set pc (mem WI addr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 14) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 13) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 12) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 11) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 10) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 9) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 8) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (sub SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr))))
    (set rn addr))
  

ldmia - Load multiple registers (postindex, increment)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x1	0x0	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set (reg WI h-gr 8) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set (reg WI h-gr 9) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set (reg WI h-gr 10) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set (reg WI h-gr 11) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set (reg WI h-gr 12) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set (reg WI h-gr 13) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set (reg WI h-gr 14) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (add SI addr 4)))))
  

ldmia-sw - Load multiple registers (postindex, increment, switch)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x1	0x1	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (add SI addr 4))
          (set (reg SI h-cpsr) (reg SI h-spsr)))))
  

ldmia-sw-wb - Load multiple registers (postindex, increment, switch, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x1	0x1	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (add SI addr 4))
          (set (reg SI h-cpsr) (reg SI h-spsr))))
    (set rn addr))
  

ldmia-wb - Load multiple registers (postindex, increment, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x0	0x1	0x0	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set (reg WI h-gr 0) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set (reg WI h-gr 1) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set (reg WI h-gr 2) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set (reg WI h-gr 3) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set (reg WI h-gr 4) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set (reg WI h-gr 5) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set (reg WI h-gr 6) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set (reg WI h-gr 7) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set (reg WI h-gr 8) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set (reg WI h-gr 9) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set (reg WI h-gr 10) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set (reg WI h-gr 11) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set (reg WI h-gr 12) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set (reg WI h-gr 13) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set (reg WI h-gr 14) (mem WI addr))
          (set addr (add SI addr 4))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set pc (mem WI addr))
          (set addr (add SI addr 4))))
    (set rn addr))
  

ldmib - Load multiple register (preindex, increment)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x1	0x0	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 8) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 9) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 10) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 11) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 12) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 13) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 14) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set pc (mem WI addr)))))
  

ldmib-sw - Load multiple register (preindex, increment, switch)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x1	0x1	0x0	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set pc (mem WI addr))
          (set (reg SI h-cpsr) (reg SI h-spsr)))))
  

ldmib-sw-wb - Load multiple registers (preindex, increment, switch, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x1	0x1	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 8) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 8 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 9) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 9 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 10) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 10 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 11) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 11 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 12) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 12 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 13) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 13 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (add SI addr 4))
          (if (and UINT reglist (sll INT 1 15))
              (set (reg WI h-gr 14) (mem WI addr))
              (set (reg WI h-gr-usr (sub INT 14 8))
                   (mem WI addr)))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set pc (mem WI addr))
          (set (reg SI h-cpsr) (reg SI h-spsr))))
    (set rn addr))
  

ldmib-wb - Load multiple registers (preindex, increment, writeback)

• machines: base


• syntax: FIXME


• format:

  31 30 29 28	27 26 25	24	23	22	21	20	19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op3	f-preindex?	f-up-down	f-load-psr?	f-write-back?	f-load?	f-rn	f-reg-list
  cond	0x4	0x1	0x1	0x0	0x1	0x1	rn	reglist



• semantics:

  (sequence
    ((WI addr))
    (set addr rn)
    (if (and UINT reglist (sll INT 1 0))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 0) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 1))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 1) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 2))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 2) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 3))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 3) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 4))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 4) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 5))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 5) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 6))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 6) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 7))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 7) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 8))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 8) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 9))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 9) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 10))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 10) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 11))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 11) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 12))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 12) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 13))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 13) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 14))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set (reg WI h-gr 14) (mem WI addr))))
    (if (and UINT reglist (sll INT 1 15))
        (sequence
          ()
          (set addr (add SI addr 4))
          (set pc (mem WI addr))))
    (set rn addr))
  

ldr-post-dec-imm-offset - Load word (postindex, decrement), immediate offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x0	0x0	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldr-post-dec-nonpriv-imm-offset - Load word (postindex, decrement, nonpriv), immediate offset

• machines: base


• syntax: ldr${cond}t $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x0	0x0	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldr-post-dec-nonpriv-reg-offset - Load word (postindex, decrement, nonpriv), register offset

• machines: base


• syntax: ldr${cond}t $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x0

  0x0

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldr-post-dec-reg-offset - Load word (postindex, decrement), register offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldr-post-inc-imm-offset - Load word (postindex, increment), immediate offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x1	0x0	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldr-post-inc-nonpriv-imm-offset - Load word (postindex, increment, nonpriv), immediate offset

• machines: base


• syntax: ldr${cond}t $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x1	0x0	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldr-post-inc-nonpriv-reg-offset - Load word (postindex, increment, nonpriv), register offset

• machines: base


• syntax: ldr${cond}t $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x1

  0x0

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldr-post-inc-reg-offset - Load word (postindex, increment), register offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldr-pre-dec-imm-offset - Load word (preindex, decrement), immediate offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x0	0x0	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr))))
  

ldr-pre-dec-reg-offset - Load word (preindex, decrement), register offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr))))
  

ldr-pre-dec-wb-imm-offset - Load word (preindex, decrement, writeback), immediate offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x0	0x0	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set rn addr))
  

ldr-pre-dec-wb-reg-offset - Load word (preindex, decrement, writeback), register offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x0

  0x0

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set rn addr))
  

ldr-pre-inc-imm-offset - Load word (preindex, increment), immediate offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x1	0x0	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr))))
  

ldr-pre-inc-reg-offset - Load word (preindex, increment), register offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr))))
  

ldr-pre-inc-wb-imm-offset - Load word (preindex, increment, writeback), immediate offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x1	0x0	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set rn addr))
  

ldr-pre-inc-wb-reg-offset - Load word (preindex, increment, writeback), register offset

• machines: base


• syntax: ldr${cond} $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x1

  0x0

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (mem SI addr))
        (set rd (mem SI addr)))
    (set rn addr))
  

ldrb-post-dec-imm-offset - Load byte (postindex, decrement), immediate offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x0	0x1	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrb-post-dec-nonpriv-imm-offset - Load byte (postindex, decrement, nonpriv), immediate offset

• machines: base


• syntax: ldr${cond}bt $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x0	0x1	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrb-post-dec-nonpriv-reg-offset - Load byte (postindex, decrement, nonpriv), register offset

• machines: base


• syntax: ldr${cond}bt $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x0

  0x1

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrb-post-dec-reg-offset - Load byte (postindex, decrement), register offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrb-post-inc-imm-offset - Load byte (postindex, increment), immediate offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x1	0x1	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrb-post-inc-nonpriv-imm-offset - Load byte (postindex, increment, nonpriv), immediate offset

• machines: base


• syntax: ldr${cond}bt $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x0	0x1	0x1	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrb-post-inc-nonpriv-reg-offset - Load byte (postindex, increment, nonpriv), register offset

• machines: base


• syntax: ldr${cond}bt $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x1

  0x1

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrb-post-inc-reg-offset - Load byte (postindex, increment), register offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x0

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrb-pre-dec-imm-offset - Load byte (preindex, decrement), immediate offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x0	0x1	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr)))))
  

ldrb-pre-dec-reg-offset - Load byte (preindex, decrement), register offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr)))))
  

ldrb-pre-dec-wb-imm-offset - Load byte (preindex, decrement, writeback), immediate offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x0	0x1	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set rn addr))
  

ldrb-pre-dec-wb-reg-offset - Load byte (preindex, decrement, writeback), register offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x0

  0x1

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set rn addr))
  

ldrb-pre-inc-imm-offset - Load byte (preindex, increment), immediate offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x1	0x1	0x0	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr)))))
  

ldrb-pre-inc-reg-offset - Load byte (preindex, increment), register offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr)))))
  

ldrb-pre-inc-wb-imm-offset - Load byte (preindex, increment, writeback), immediate offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28	27 26	25	24	23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-preindex?	f-up-down	f-byte-qty?	f-write-back?	f-load?	f-rn	f-rd	f-uimm12
  cond	0x1	0x0	0x1	0x1	0x1	0x1	0x1	rn	rd	uimm12



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset uimm12)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set rn addr))
  

ldrb-pre-inc-wb-reg-offset - Load byte (preindex, increment, writeback), register offset

• machines: base


• syntax: ldr${cond}b $rd,???


• format:

  31 30 29 28

  27 26

  25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8 7

  6 5

  4

  3 2 1 0

  f-cond

  f-op2

  f-imm?

  f-preindex?

  f-up-down

  f-byte-qty?

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-operand2-shiftimm

  f-operand2-shifttype

  f-operand2-reg?

  f-rm

  cond

  0x1

  0x1

  0x1

  0x1

  0x1

  0x1

  0x1

  rn

  rd

  operand2-shiftimm

  operand2-shifttype

  0x0

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem QI addr)))
        (set rd (zext SI (mem QI addr))))
    (set rn addr))
  

ldrh-post-dec-imm-offset - Load halfword (postdecrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x0

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x0

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrh-post-dec-reg-offset - Load halfword (postdecrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x0

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x0

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrh-post-inc-imm-offset - Load halfword (postincrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x0

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x0

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrh-post-inc-reg-offset - Load halfword (postincrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x0

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x0

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrh-pre-dec-imm-offset - Load halfword (predecrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x0

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr)))))
  

ldrh-pre-dec-reg-offset - Load halfword (predecrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x0

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr)))))
  

ldrh-pre-dec-wb-imm-offset - Load halfword (predec, writeback), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x0

  0x1

  0x1

  0x1

  rn

  rd

  0x1

  0x0

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set rn addr))
  

ldrh-pre-dec-wb-reg-offset - Load halfword (predec, writeback), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x0

  0x0

  0x1

  0x1

  rn

  rd

  0x0

  0x1

  0x0

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set rn addr))
  

ldrh-pre-inc-imm-offset - Load halfword (preincrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x0

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr)))))
  

ldrh-pre-inc-reg-offset - Load halfword (preincrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x0

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr)))))
  

ldrh-pre-inc-wb-imm-offset - Load halfword (preinc, writeback), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x1

  0x1

  0x1

  0x1

  rn

  rd

  0x1

  0x0

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set rn addr))
  

ldrh-pre-inc-wb-reg-offset - Load halfword (preinc, writeback), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x1

  0x0

  0x1

  0x1

  rn

  rd

  0x0

  0x1

  0x0

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (zext SI (mem HI addr)))
        (set rd (zext SI (mem HI addr))))
    (set rn addr))
  

ldrsb-post-dec-imm-offset - Load signed byte (postdecrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x0

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x0

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrsb-post-dec-reg-offset - Load signed byte (postdecrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x0

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x0

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrsb-post-inc-imm-offset - Load signed byte (postindex, increment), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x0

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x0

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrsb-post-inc-reg-offset - Load signed byte (postindex, increment), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x0

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x0

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrsb-pre-dec-imm-offset - Load signed byte (predecrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x0

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr)))))
  

ldrsb-pre-dec-reg-offset - Load signed byte (predecrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x0

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr)))))
  

ldrsb-pre-dec-wb-imm-offset - Load signed byte (predec, writeback), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x0

  0x1

  0x1

  0x1

  rn

  rd

  0x1

  0x1

  0x0

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set rn addr))
  

ldrsb-pre-dec-wb-reg-offset - Load signed byte (predec, writeback), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x0

  0x0

  0x1

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x0

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set rn addr))
  

ldrsb-pre-inc-imm-offset - Load signed byte (preincrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x0

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr)))))
  

ldrsb-pre-inc-reg-offset - Load signed byte (preincrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x0

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr)))))
  

ldrsb-pre-inc-wb-imm-offset - Load signed byte (preinc, writeback), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x1

  0x1

  0x1

  0x1

  rn

  rd

  0x1

  0x1

  0x0

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set rn addr))
  

ldrsb-pre-inc-wb-reg-offset - Load signed byte (preinc, writeback), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x1

  0x0

  0x1

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x0

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem QI addr)))
        (set rd (ext SI (mem QI addr))))
    (set rn addr))
  

ldrsh-post-dec-imm-offset - Load signed halfword (postdecrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x0

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrsh-post-dec-reg-offset - Load signed halfword (postdecrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x0

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set addr (sub SI rn offset))
    (set rn addr))
  

ldrsh-post-inc-imm-offset - Load signed halfword (postincrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x0

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrsh-post-inc-reg-offset - Load signed halfword (postincrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x0

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr rn)
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set addr (add SI rn offset))
    (set rn addr))
  

ldrsh-pre-dec-imm-offset - Load signed halfword (predecrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x0

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr)))))
  

ldrsh-pre-dec-reg-offset - Load signed halfword (predecrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x0

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr)))))
  

ldrsh-pre-dec-wb-imm-offset - Load signed halfword (predec, writeback), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x0

  0x1

  0x1

  0x1

  rn

  rd

  0x1

  0x1

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set rn addr))
  

ldrsh-pre-dec-wb-reg-offset - Load signed halfword (predec, writeback), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x0

  0x0

  0x1

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (sub SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set rn addr))
  

ldrsh-pre-inc-imm-offset - Load signed halfword (preincrement), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x1

  0x1

  0x0

  0x1

  rn

  rd

  0x1

  0x1

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr)))))
  

ldrsh-pre-inc-reg-offset - Load signed halfword (preincrement), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x1

  0x0

  0x0

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr)))))
  

ldrsh-pre-inc-wb-imm-offset - Load signed halfword (preinc, writeback), immediate offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11

  10

  9

  8

  7 6 5 4 3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-hdt-offset8

  cond

  0x0

  0x1

  0x1

  0x1

  0x1

  0x1

  rn

  rd

  0x1

  0x1

  0x1

  0x1

  hdt-offset8



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset hdt-offset8)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set rn addr))
  

ldrsh-pre-inc-wb-reg-offset - Load signed halfword (preinc, writeback), register offset

• machines: base


• syntax: FIXME


• format:

  31 30 29 28

  27 26 25

  24

  23

  22

  21

  20

  19 18 17 16

  15 14 13 12

  11 10 9 8

  7

  6

  5

  4

  3 2 1 0

  f-cond

  f-op3

  f-preindex?

  f-up-down

  f-bit22

  f-write-back?

  f-load?

  f-rn

  f-rd

  f-offset4-hi

  f-bit7

  f-signed?

  f-halfword?

  f-bit4

  f-rm

  cond

  0x0

  0x1

  0x1

  0x0

  0x1

  0x1

  rn

  rd

  0x0

  0x1

  0x1

  0x1

  0x1

  rm



• semantics:

  (sequence
    ((SI addr) (SI offset))
    (set offset rm)
    (set addr (add SI rn offset))
    (if (eq f-rd 15)
        (set pc (ext SI (mem HI addr)))
        (set rd (ext SI (mem HI addr))))
    (set rn addr))
  

mla - Multiply and accumulate

• machines: base


• syntax: mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn}


• format:

  31 30 29 28	27 26 25 24 23 22	21	20	19 18 17 16	15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-cond	f-op6	f-acc?	f-set-cc?	f-mul-rd	f-mul-rn	f-rs	f-op-mul	f-rm
  cond	0x0	0x1	set-cc?	mul-rd	mul-rn	rs	0x9	rm



• semantics:

  (sequence
    ((WI result))
    (set mul-rd (add SI (mul SI rm rs) mul-rn))
    (if set-cc?
        (sequence
          ()
          (set zbit (eq result 0))
          (set nbit (lt result 0)))))
  

mov-imm - Move immediate

• machines: base


• syntax: mov$cond${set-cc?} $rd,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0xd	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result imm12)
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (set zbit (eq result 0))
                (set nbit (lt result 0)))))))
  

mov-reg/imm-shift - Move immediate shift

• machines: base


• syntax: mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xd	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm
           cbit))
    (set result operand2)
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

mov-reg/reg-shift - Move register shift

• machines: base


• syntax: mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xd	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg
           cbit))
    (set result operand2)
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

mrs-c - Transfer CPSR contents to a register

• machines: base


• syntax: mrs$cond $rd,cpsr


• format:

  31 30 29 28	27 26 25 24 23	22	21 20 19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op5	f-psr	f-op-mrs1	f-rd	f-op-mrs2
  cond	0x2	0x0	0xf	rd	0x0



• semantics:

  (set rd (reg SI h-cpsr))
  

mrs-s - Transfer SPSR contents to a register

• machines: base


• syntax: mrs$cond $rd,spsr


• format:

  31 30 29 28	27 26 25 24 23	22	21 20 19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op5	f-psr	f-op-mrs1	f-rd	f-op-mrs2
  cond	0x2	0x1	0xf	rd	0x0



• semantics:

  (set rd (reg SI h-spsr))
  

msr-c - Transfer register contents to CPSR

• machines: base


• syntax: msr$cond cpsr,$rm


• format:

  31 30 29 28	27 26 25 24 23	22	21 20 19 18 17 16 15 14 13 12	11 10 9 8 7 6 5 4	3 2 1 0
  f-cond	f-op5	f-psr	f-op-msr1	f-op-msr2	f-rm
  cond	0x2	0x0	0x29f	0x0	rm



• semantics:

  (set (reg SI h-cpsr) rm)
  

msr-s - Transfer register contents to SPSR

• machines: base


• syntax: msr$cond spsr,$rm


• format:

  31 30 29 28	27 26 25 24 23	22	21 20 19 18 17 16 15 14 13 12	11 10 9 8 7 6 5 4	3 2 1 0
  f-cond	f-op5	f-psr	f-op-msr1	f-op-msr2	f-rm
  cond	0x2	0x1	0x29f	0x0	rm



• semantics:

  (set (reg SI h-spsr) rm)
  

mul - Multiply

• machines: base


• syntax: mul$cond${set-cc?} ${mul-rd},$rm,$rs


• format:

  31 30 29 28	27 26 25 24 23 22	21	20	19 18 17 16	15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-cond	f-op6	f-acc?	f-set-cc?	f-mul-rd	f-mul-rn	f-rs	f-op-mul	f-rm
  cond	0x0	0x0	set-cc?	mul-rd	mul-rn	rs	0x9	rm



• semantics:

  (sequence
    ((WI result))
    (set result (mul SI rm rs))
    (set mul-rd result)
    (if set-cc?
        (sequence
          ()
          (set zbit (eq result 0))
          (set nbit (lt result 0)))))
  

mvn-imm - Move (logical) negate immediate

• machines: base


• syntax: mvn$cond${set-cc?} $rd,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0xf	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (inv UINT imm12))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (set zbit (eq result 0))
                (set nbit (lt result 0)))))))
  

mvn-reg/imm-shift - Move negate immediate shift

• machines: base


• syntax: mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xf	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm
           cbit))
    (set result (inv SI operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

mvn-reg/reg-shift - Move negate register shift

• machines: base


• syntax: mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xf	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg
           cbit))
    (set result (inv SI operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

orr-imm - Bitwise OR immediate

• machines: base


• syntax: orr$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0xc	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (or SI rn imm12))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (set zbit (eq result 0))
                (set nbit (lt result 0)))))))
  

orr-reg/imm-shift - Bitwise OR immediate shift

• machines: base


• syntax: orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xc	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm
           cbit))
    (set result (or SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

orr-reg/reg-shift - Bitwise OR register shift

• machines: base


• syntax: orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0xc	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2) (BI carry-out) (SI result))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set carry-out
         (c-call
           BI
           "compute_carry_out_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg
           cbit))
    (set result (or SI rn operand2))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ()
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit carry-out))))))
  

rsb-imm - Reverse subtract immediate

• machines: base


• syntax: rsb$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x3	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (sub UINT imm12 rn))
    (if (eq f-rd 15)
        (sequence
          ()
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr)))
          (set pc result))
        (sequence
          ()
          (if set-cc?
              (sequence
                ((SI result))
                (set result (subc UINT imm12 rn 0))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit (not BI (sub-cflag UINT imm12 rn 0)))
                (set vbit (sub-oflag UINT imm12 rn 0))))
          (set rd result))))
  

rsb-reg/imm-shift - Reverse subtract immediate shift

• machines: base


• syntax: rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x3	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (sub SI operand2 rn))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result (subc SI temp-op2 temp-op1 0))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI (sub-cflag SI temp-op2 temp-op1 0)))
                (set vbit (sub-oflag SI temp-op2 temp-op1 0)))))))
  

rsb-reg/reg-shift - Reverse subtract register shift

• machines: base


• syntax: rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x3	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (sub SI operand2 rn))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result (subc SI temp-op2 temp-op1 0))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI (sub-cflag SI temp-op2 temp-op1 0)))
                (set vbit (sub-oflag SI temp-op2 temp-op1 0)))))))
  

rsc-imm - Reverse subtract with carry immediate

• machines: base


• syntax: rsc$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x7	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (subc UINT imm12 rn (not BI cbit)))
    (if (eq f-rd 15)
        (sequence
          ()
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr)))
          (set pc result))
        (sequence
          ()
          (if set-cc?
              (sequence
                ((SI result))
                (set result (subc UINT imm12 rn (not BI cbit)))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI (sub-cflag UINT imm12 rn (not BI cbit))))
                (set vbit
                     (sub-oflag UINT imm12 rn (not BI cbit)))))
          (set rd result))))
  

rsc-reg/imm-shift - Reverse subtract with carry immediate shift

• machines: base


• syntax: rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x7	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (subc SI operand2 rn (not BI cbit)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result
                     (subc SI temp-op2 temp-op1 (not BI cbit)))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI
                          (sub-cflag SI temp-op2 temp-op1 (not BI cbit))))
                (set vbit
                     (sub-oflag SI temp-op2 temp-op1 (not BI cbit))))))))
  

rsc-reg/reg-shift - Reverse subtract with carry register shift

• machines: base


• syntax: rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x7	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (subc SI operand2 rn (not BI cbit)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result
                     (subc SI temp-op2 temp-op1 (not BI cbit)))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI
                          (sub-cflag SI temp-op2 temp-op1 (not BI cbit))))
                (set vbit
                     (sub-oflag SI temp-op2 temp-op1 (not BI cbit))))))))
  

sbc-imm - Subtract with carry immediate

• machines: base


• syntax: sbc$cond${set-cc?} $rd,$rn,$imm12


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7 6 5 4 3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-imm12
  cond	0x0	0x1	0x6	set-cc?	rn	rd	imm12



• semantics:

  (sequence
    ((SI result))
    (set result (subc SI rn imm12 (not BI cbit)))
    (if (eq f-rd 15)
        (sequence
          ()
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr)))
          (set pc result))
        (sequence
          ()
          (if set-cc?
              (sequence
                ((SI result))
                (set result (subc SI rn imm12 (not BI cbit)))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI (sub-cflag SI rn imm12 (not BI cbit))))
                (set vbit (sub-oflag SI rn imm12 (not BI cbit)))))
          (set rd result))))
  

sbc-reg/imm-shift - Subtract with carry immediate shift

• machines: base


• syntax: sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8 7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftimm	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x6	set-cc?	rn	rd	operand2-shiftimm	operand2-shifttype	0x0	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_immshift"
           rm
           operand2-shifttype
           operand2-shiftimm))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (subc SI rn operand2 (not BI cbit)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result
                     (subc SI temp-op1 temp-op2 (not BI cbit)))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI
                          (sub-cflag SI temp-op1 temp-op2 (not BI cbit))))
                (set vbit
                     (sub-oflag SI temp-op1 temp-op2 (not BI cbit))))))))
  

sbc-reg/reg-shift - Subtract with carry register shift

• machines: base


• syntax: sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}


• format:

  31 30 29 28	27 26	25	24 23 22 21	20	19 18 17 16	15 14 13 12	11 10 9 8	7	6 5	4	3 2 1 0
  f-cond	f-op2	f-imm?	f-op-alu	f-set-cc?	f-rn	f-rd	f-operand2-shiftreg	f-bit7	f-operand2-shifttype	f-operand2-reg?	f-rm
  cond	0x0	0x0	0x6	set-cc?	rn	rd	operand2-shiftreg	0x0	operand2-shifttype	0x1	rm



• semantics:

  (sequence
    ((SI operand2)
     (SI result)
     (SI temp-op1)
     (SI temp-op2))
    (set operand2
         (c-call
           SI
           "compute_operand2_regshift"
           rm
           operand2-shifttype
           operand2-shiftreg))
    (set temp-op1 rn)
    (set temp-op2 operand2)
    (set result (subc SI rn operand2 (not BI cbit)))
    (if (eq f-rd 15)
        (sequence
          ()
          (set pc result)
          (if set-cc?
              (set (reg SI h-cpsr) (reg SI h-spsr))))
        (sequence
          ()
          (set rd result)
          (if set-cc?
              (sequence
                ((SI result))
                (set result
                     (subc SI temp-op1 temp-op2 (not BI cbit)))
                (sequence
                  ()
                  (set zbit (eq result 0))
                  (set nbit (lt result 0)))
                (set cbit
                     (not BI
                          (sub-cflag SI temp-op1 temp-op2 (not BI cbit))))
                (set vbit
                     (sub-oflag SI temp-op1 temp-op2 (not BI cbit))))))))
  

smlal - Multiply long and accumulate (signed)

• machines: base


• syntax: smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs


• format:

  31 30 29 28	27 26 25 24 23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-cond	f-op5	f-unsigned?	f-acc?	f-set-cc?	f-rdhi	f-rdlo	f-rs	f-op-mul	f-rm
  cond	0x1	0x1	0x1	set-cc?	rdhi	rdlo	rs	0x9	rm



• semantics:

  (sequence
    ((DI mul-result) (SI hi) (SI lo))
    (set mul-result (join DI SI rdhi rdlo))
    (set mul-result
         (add DI
              (mul DI (ext DI rs) (ext DI rm))
              mul-result))
    (set rdhi (subword SI mul-result 0))
    (set rdlo (subword SI mul-result 1))
    (if set-cc?
        (sequence
          ()
          (set zbit (eq mul-result 0))
          (set nbit (lt mul-result 0)))))
  

smull - Multiply long (signed)

• machines: base


• syntax: smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs


• format:

  31 30 29 28	27 26 25 24 23	22	21	20	19 18 17 16	15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-cond	f-op5	f-unsigned?	f-acc?	f-set-cc?	f-rdhi	f-rdlo	f-rs	f-op-mul	f-rm
  cond	0x1	0x1	0x0	set-cc?	rdhi	rdlo	rs	0x9	rm



• semantics:

  (sequence
    ((DI mul-result) (SI hi) (SI lo))
    (set mul-result (mul DI (ext DI rs) (ext DI rm)))
    (set rdhi (subword SI mul-result 0))
    (set rdlo (subword SI mul-result 1))
    (if set-cc?
        (sequence
          ()
          (set zbit (eq mul-result 0))
          (set nbit (lt mul-result 0)))))