15 14 13 12 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op5 | f-i | f-addsub-op | f-rn | f-rs | f-rd |
0x3 | 0x0 | 0x0 | rn | rs | rd |
(sequence () (sequence ((SI result)) (set result (addc SI rs rn 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rs rn 0)) (set vbit (add-oflag SI rs rn 0))) (set rd (add SI rs rn)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x0 | 0x1 | 0x1 | hs | hd |
(if (eq (index-of hd) 7) (set pc (add SI hd hs)) (set hd (add SI hd hs)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x0 | 0x1 | 0x0 | rs | hd |
(if (eq (index-of hd) 7) (set pc (add SI hd rs)) (set hd (add SI hd rs)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x0 | 0x0 | 0x1 | hs | rd |
(set rd (add SI rd hs))
15 14 13 12 11 10 9 8 | 7 | 6 5 4 3 2 1 0 |
f-op8 | f-addoff-s | f-sword7 |
0xb0 | 0x0 | sword7 |
(set sp (add SI sp sword7))
15 14 13 12 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op5 | f-i | f-addsub-op | f-offset3 | f-rs | f-rd |
0x3 | 0x1 | 0x0 | offset3 | rs | rd |
(sequence () (sequence ((SI result)) (set result (addc SI rs offset3 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rs offset3 0)) (set vbit (add-oflag SI rs offset3 0))) (set rd (add SI rs offset3)))
15 14 13 | 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op3 | f-mcasi-op | f-bit10-rd | f-offset8 |
0x1 | 0x2 | bit10-rd | offset8 |
(sequence () (sequence ((SI result)) (set result (addc SI bit10-rd offset8 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI bit10-rd offset8 0)) (set vbit (add-oflag SI bit10-rd offset8 0))) (set bit10-rd (add SI bit10-rd offset8)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x5 | rs | rd |
(sequence ((SI result)) (set result (addc SI rd rs cbit)) (sequence ((SI result)) (set result (addc SI rd rs cbit)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rd rs cbit)) (set vbit (add-oflag SI rd rs cbit))) (set rd result))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x0 | rs | rd |
(sequence () (set rd (and SI rd rs)) (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x4 | rs | rd |
(sequence ((BI carry-out) (SI result)) (set carry-out (c-call BI "compute_carry_out_regshift" rd (enum INT SHIFT-TYPE-asr) rs cbit)) (set result (sra SI rd rs)) (set rd result) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0xe | rs | rd |
(sequence () (set rd (and SI rd (inv SI rs))) (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0xb | rs | rd |
(sequence ((SI result)) (set result (addc SI rd rs 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (add-cflag SI rd rs 0)) (set vbit (add-oflag SI rd rs 0)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0xa | rs | rd |
(sequence ((SI result)) (set result (subc SI rd rs 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rd rs 0))) (set vbit (sub-oflag SI rd rs 0)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x1 | rs | rd |
(sequence () (set rd (xor SI rd rs)) (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x2 | rs | rd |
(sequence ((BI carry-out) (SI result)) (set carry-out (c-call BI "compute_carry_out_regshift" rd (enum INT SHIFT-TYPE-lsl) rs cbit)) (set result (sll SI rd rs)) (set rd result) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x3 | rs | rd |
(sequence ((BI carry-out) (SI result)) (set carry-out (c-call BI "compute_carry_out_regshift" rd (enum INT SHIFT-TYPE-lsr) rs cbit)) (set result (srl SI rd rs)) (set rd result) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0xd | rs | rd |
(sequence () (set rd (mul SI rd rs)) (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0xf | rs | rd |
(sequence () (set rd (inv SI rs)) (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x9 | rs | rd |
(sequence ((SI result)) (set result (neg SI rs)) (sequence ((SI result)) (set result (subc INT 0 rs 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag INT 0 rs 0))) (set vbit (sub-oflag INT 0 rs 0))) (set rd result))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0xc | rs | rd |
(sequence () (set rd (or SI rd rs)) (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x7 | rs | rd |
(sequence ((BI carry-out) (SI result)) (set carry-out (c-call BI "compute_carry_out_regshift" rd (enum INT SHIFT-TYPE-ror) rs cbit)) (set result (ror SI rd rs)) (set rd result) (sequence () (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit carry-out)))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x6 | rs | rd |
(sequence ((SI result)) (set result (subc SI rd rs (not BI cbit))) (sequence ((SI result)) (set result (subc SI rd rs (not BI cbit))) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rd rs (not BI cbit)))) (set vbit (sub-oflag SI rd rs (not BI cbit)))) (set rd result))
15 14 13 12 11 10 | 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op6 | f-alu-op | f-rs | f-rd |
0x10 | 0x8 | rs | rd |
(sequence ((SI x)) (set x (and SI rd rs)) (sequence () (set zbit (eq x 0)) (set nbit (lt x 0))))
15 14 13 | 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-shift-op | f-offset5 | f-rs | f-rd |
0x0 | 0x2 | offset5 | rs | rd |
(sequence ((BI carry-out)) (set carry-out (c-call BI "compute_carry_out_immshift" rs (enum INT SHIFT-TYPE-asr) offset5 cbit)) (set rd (sra SI rs offset5)) (sequence () (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))) (set cbit carry-out)))
15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-op5 | f-offset11 |
0x1c | offset11 |
(set pc offset11)
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x3 | soffset8 |
(if (not BI cbit) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x2 | soffset8 |
(if cbit (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x0 | soffset8 |
(if zbit (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0xa | soffset8 |
(if (not BI (xor BI nbit vbit)) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0xc | soffset8 |
(if (not BI (or BI zbit (xor BI nbit vbit))) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x8 | soffset8 |
(if (and BI cbit (not BI zbit)) (set pc soffset8))
15 14 13 12 | 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-op4 | f-lbwl-h | f-lbwl-hi |
0xf | 0x0 | lbwl-hi |
(set lr (add USI (add USI pc 4) (sll INT lbwl-hi 12)))
15 14 13 12 | 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-op4 | f-lbwl-h | f-lbwl-lo |
0xf | 0x1 | lbwl-lo |
(sequence ((WI cur-pc)) (set cur-pc pc) (set pc (add SI lr (sll UINT lbwl-lo 1))) (set lr (or SI (add SI cur-pc 2) 1)))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0xd | soffset8 |
(if (or BI zbit (xor BI nbit vbit)) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x9 | soffset8 |
(if (or BI (not BI cbit) zbit) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0xb | soffset8 |
(if (xor BI nbit vbit) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x4 | soffset8 |
(if nbit (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x1 | soffset8 |
(if (not BI zbit) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x5 | soffset8 |
(if (not BI nbit) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x7 | soffset8 |
(if (not BI vbit) (set pc soffset8))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-cond | f-soffset8 |
0xd | 0x6 | soffset8 |
(if vbit (set pc soffset8))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x3 | 0x0 | 0x1 | hs | 0x0 |
(sequence () (set pc hs) (if (not SI (and SI hs 1)) (set (reg BI h-tbit) 0)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x3 | 0x0 | 0x0 | rs | 0x0 |
(sequence () (set pc rs) (if (not SI (and SI rs 1)) (set (reg BI h-tbit) 0)))
15 14 13 | 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op3 | f-mcasi-op | f-bit10-rd | f-offset8 |
0x1 | 0x1 | bit10-rd | offset8 |
(sequence ((SI result)) (set result (subc SI bit10-rd offset8 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI bit10-rd offset8 0))) (set vbit (sub-oflag SI bit10-rd offset8 0)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x1 | 0x1 | 0x1 | hs | hd |
(sequence ((SI result)) (set result (subc SI hd hs 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI hd hs 0))) (set vbit (sub-oflag SI hd hs 0)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x1 | 0x1 | 0x0 | rs | hd |
(sequence ((SI result)) (set result (subc SI hd rs 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI hd rs 0))) (set vbit (sub-oflag SI hd rs 0)))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x1 | 0x0 | 0x1 | hs | rd |
(sequence ((SI result)) (set result (subc SI rd hs 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rd hs 0))) (set vbit (sub-oflag SI rd hs 0)))
15 14 13 12 | 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-sp | f-bit10-rd | f-word8 |
0xa | 0x0 | bit10-rd | word8 |
(set bit10-rd (add USI (and USI (add USI pc 4) -4) word8))
15 14 13 12 | 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-sp | f-bit10-rd | f-word8 |
0xa | 0x1 | bit10-rd | word8 |
(set bit10-rd (add SI sp word8))
15 14 13 12 | 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-bit10-rb | f-rlist |
0xc | 0x1 | bit10-rb | rlist |
(sequence () (if (and UINT rlist (sll INT 1 0)) (sequence () (set (reg WI h-gr-t 0) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 1)) (sequence () (set (reg WI h-gr-t 1) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 2)) (sequence () (set (reg WI h-gr-t 2) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 3)) (sequence () (set (reg WI h-gr-t 3) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 4)) (sequence () (set (reg WI h-gr-t 4) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 5)) (sequence () (set (reg WI h-gr-t 5) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 6)) (sequence () (set (reg WI h-gr-t 6) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 7)) (sequence () (set (reg WI h-gr-t 7) (mem WI bit10-rb)) (set bit10-rb (add SI bit10-rb 4)))))
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-l | f-b | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x1 | 0x0 | 0x0 | ro | rb | rd |
(set rd (mem WI (add SI rb ro)))
15 14 13 | 12 | 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-b-imm | f-l | f-offset5-7 | f-rb | f-rd |
0x3 | 0x0 | 0x1 | offset5-7 | rb | rd |
(set rd (mem WI (add SI rb offset5-7)))
15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op5 | f-bit10-rd | f-word8 |
0x9 | bit10-rd | word8 |
(set bit10-rd (mem WI (add USI (and USI (add USI pc 4) -4) word8)))
15 14 13 12 | 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-bit10-rd | f-word8 |
0x9 | 0x1 | bit10-rd | word8 |
(set bit10-rd (mem WI (add SI sp word8)))
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-l | f-b | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x1 | 0x1 | 0x0 | ro | rb | rd |
(set rd (zext SI (mem QI (add SI rb ro))))
15 14 13 | 12 | 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-b-imm | f-l | f-offset5 | f-rb | f-rd |
0x3 | 0x1 | 0x1 | offset5 | rb | rd |
(set rd (zext SI (mem QI (add SI rb offset5))))
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-h | f-s | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x1 | 0x0 | 0x1 | ro | rb | rd |
(set rd (zext SI (mem HI (add SI rb ro))))
15 14 13 12 | 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-l | f-offset5-6 | f-rb | f-rd |
0x8 | 0x1 | offset5-6 | rb | rd |
(set rd (zext WI (mem HI (add SI rb offset5-6))))
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-h | f-s | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x0 | 0x1 | 0x1 | ro | rb | rd |
(set rd (ext SI (mem QI (add SI rb ro))))
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-h | f-s | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x1 | 0x1 | 0x1 | ro | rb | rd |
(set rd (ext SI (mem HI (add SI rb ro))))
15 14 13 | 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-shift-op | f-offset5 | f-rs | f-rd |
0x0 | 0x0 | offset5 | rs | rd |
(sequence ((BI carry-out)) (set carry-out (c-call BI "compute_carry_out_immshift" rs (enum INT SHIFT-TYPE-lsl) offset5 cbit)) (set rd (sll SI rs offset5)) (sequence () (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))) (set cbit carry-out)))
15 14 13 | 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-shift-op | f-offset5 | f-rs | f-rd |
0x0 | 0x1 | offset5 | rs | rd |
(sequence ((BI carry-out)) (set carry-out (c-call BI "compute_carry_out_immshift" rs (enum INT SHIFT-TYPE-lsr) offset5 cbit)) (set rd (srl SI rs offset5)) (sequence () (sequence () (set zbit (eq rd 0)) (set nbit (lt rd 0))) (set cbit carry-out)))
15 14 13 | 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op3 | f-mcasi-op | f-bit10-rd | f-offset8 |
0x1 | 0x0 | bit10-rd | offset8 |
(sequence () (set bit10-rd offset8) (sequence () (set zbit (eq bit10-rd 0)) (set nbit (lt bit10-rd 0))))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x2 | 0x1 | 0x1 | hs | hd |
(if (eq (index-of hd) 7) (set pc hs) (set hd hs))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x2 | 0x1 | 0x0 | rs | hd |
(if (eq (index-of hd) 7) (set pc rs) (set hd rs))
15 14 13 12 11 10 | 9 8 | 7 | 6 | 5 4 3 | 2 1 0 |
f-op6 | f-hireg-op | f-h1 | f-h2 | f-rs | f-rd |
0x11 | 0x2 | 0x0 | 0x1 | hs | rd |
(set rd hs)
15 14 13 12 | 11 | 10 9 | 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-pushpop-op | f-r | f-rlist |
0xb | 0x1 | 0x2 | 0x0 | rlist |
(sequence () (if (and UINT rlist (sll INT 1 0)) (sequence () (set (reg WI h-gr-t 0) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 1)) (sequence () (set (reg WI h-gr-t 1) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 2)) (sequence () (set (reg WI h-gr-t 2) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 3)) (sequence () (set (reg WI h-gr-t 3) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 4)) (sequence () (set (reg WI h-gr-t 4) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 5)) (sequence () (set (reg WI h-gr-t 5) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 6)) (sequence () (set (reg WI h-gr-t 6) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 7)) (sequence () (set (reg WI h-gr-t 7) (mem WI sp)) (set sp (add SI sp 4)))))
15 14 13 12 | 11 | 10 9 | 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-pushpop-op | f-r | f-rlist |
0xb | 0x1 | 0x2 | 0x1 | rlist |
(sequence () (if (and UINT rlist (sll INT 1 0)) (sequence () (set (reg WI h-gr-t 0) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 1)) (sequence () (set (reg WI h-gr-t 1) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 2)) (sequence () (set (reg WI h-gr-t 2) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 3)) (sequence () (set (reg WI h-gr-t 3) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 4)) (sequence () (set (reg WI h-gr-t 4) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 5)) (sequence () (set (reg WI h-gr-t 5) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 6)) (sequence () (set (reg WI h-gr-t 6) (mem WI sp)) (set sp (add SI sp 4)))) (if (and UINT rlist (sll INT 1 7)) (sequence () (set (reg WI h-gr-t 7) (mem WI sp)) (set sp (add SI sp 4)))) (set pc (mem WI sp)) (set sp (add SI sp 4)))
15 14 13 12 | 11 | 10 9 | 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-pushpop-op | f-r | f-rlist |
0xb | 0x0 | 0x2 | 0x0 | rlist |
(sequence () (if (and UINT rlist (sll INT 1 7)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 7)))) (if (and UINT rlist (sll INT 1 6)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 6)))) (if (and UINT rlist (sll INT 1 5)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 5)))) (if (and UINT rlist (sll INT 1 4)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 4)))) (if (and UINT rlist (sll INT 1 3)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 3)))) (if (and UINT rlist (sll INT 1 2)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 2)))) (if (and UINT rlist (sll INT 1 1)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 1)))) (if (and UINT rlist (sll INT 1 0)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 0)))))
15 14 13 12 | 11 | 10 9 | 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-pushpop-op | f-r | f-rlist |
0xb | 0x0 | 0x2 | 0x1 | rlist |
(sequence () (set sp (sub SI sp 4)) (set (mem WI sp) lr) (if (and UINT rlist (sll INT 1 7)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 7)))) (if (and UINT rlist (sll INT 1 6)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 6)))) (if (and UINT rlist (sll INT 1 5)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 5)))) (if (and UINT rlist (sll INT 1 4)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 4)))) (if (and UINT rlist (sll INT 1 3)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 3)))) (if (and UINT rlist (sll INT 1 2)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 2)))) (if (and UINT rlist (sll INT 1 1)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 1)))) (if (and UINT rlist (sll INT 1 0)) (sequence () (set sp (sub SI sp 4)) (set (mem WI sp) (reg WI h-gr-t 0)))))
15 14 13 12 | 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-bit10-rb | f-rlist |
0xc | 0x0 | bit10-rb | rlist |
(sequence () (if (and UINT rlist (sll INT 1 0)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 0)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 1)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 1)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 2)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 2)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 3)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 3)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 4)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 4)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 5)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 5)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 6)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 6)) (set bit10-rb (add SI bit10-rb 4)))) (if (and UINT rlist (sll INT 1 7)) (sequence () (set (mem WI bit10-rb) (reg WI h-gr-t 7)) (set bit10-rb (add SI bit10-rb 4)))))
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-l | f-b | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x0 | 0x0 | 0x0 | ro | rb | rd |
(set (mem WI (add SI rb ro)) rd)
15 14 13 | 12 | 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-b-imm | f-l | f-offset5-7 | f-rb | f-rd |
0x3 | 0x0 | 0x0 | offset5-7 | rb | rd |
(set (mem WI (add SI rb offset5-7)) rd)
15 14 13 12 | 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op4 | f-l | f-bit10-rd | f-word8 |
0x9 | 0x0 | bit10-rd | word8 |
(set (mem WI (add SI sp word8)) bit10-rd)
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-l | f-b | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x0 | 0x1 | 0x0 | ro | rb | rd |
(set (mem QI (add SI rb ro)) rd)
15 14 13 | 12 | 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op3 | f-b-imm | f-l | f-offset5 | f-rb | f-rd |
0x3 | 0x1 | 0x0 | offset5 | rb | rd |
(set (mem QI (add SI rb offset5)) rd)
15 14 13 12 | 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-h | f-s | f-bit9 | f-ro | f-rb | f-rd |
0x5 | 0x0 | 0x0 | 0x1 | ro | rb | rd |
(set (mem HI (add SI rb ro)) rd)
15 14 13 12 | 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-op4 | f-l | f-offset5-6 | f-rb | f-rd |
0x8 | 0x0 | offset5-6 | rb | rd |
(set (mem HI (add SI rb offset5-6)) rd)
15 14 13 12 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op5 | f-i | f-addsub-op | f-rn | f-rs | f-rd |
0x3 | 0x0 | 0x1 | rn | rs | rd |
(sequence () (sequence ((SI result)) (set result (subc SI rs rn 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rs rn 0))) (set vbit (sub-oflag SI rs rn 0))) (set rd (sub SI rs rn)))
15 14 13 12 11 10 9 8 | 7 | 6 5 4 3 2 1 0 |
f-op8 | f-addoff-s | f-sword7 |
0xb0 | 0x1 | sword7 |
(set sp (sub SI sp sword7))
15 14 13 12 11 | 10 | 9 | 8 7 6 | 5 4 3 | 2 1 0 |
f-op5 | f-i | f-addsub-op | f-offset3 | f-rs | f-rd |
0x3 | 0x1 | 0x1 | offset3 | rs | rd |
(sequence () (sequence ((SI result)) (set result (subc SI rs offset3 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI rs offset3 0))) (set vbit (sub-oflag SI rs offset3 0))) (set rd (sub SI rs offset3)))
15 14 13 | 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op3 | f-mcasi-op | f-bit10-rd | f-offset8 |
0x1 | 0x3 | bit10-rd | offset8 |
(sequence () (sequence ((SI result)) (set result (subc SI bit10-rd offset8 0)) (sequence () (set zbit (eq result 0)) (set nbit (lt result 0))) (set cbit (not BI (sub-cflag SI bit10-rd offset8 0))) (set vbit (sub-oflag SI bit10-rd offset8 0))) (set bit10-rd (sub SI bit10-rd offset8)))
15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-op8 | f-value8 |
0xdf | value8 |
(set pc (c-call WI "thumb_swi" pc value8))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/