EPIPHANY Instruction Documentation

Instructions

Instructions for each machine:

epiphany32 - Adapteva EPIPHANY

ALU - ALU
BR - Branch
alphabetically

Individual instructions descriptions

add - add

machines: base

syntax: add $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x1	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (add-cflag SI rn6 rm6 0))
      (set vbit (add-oflag SI rn6 rm6 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd6 (add SI rn6 rm6))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

add16 - add

machines: base

syntax: add $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x1 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (add-cflag SI rn rm 0))
      (set vbit (add-oflag SI rn rm 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd (add SI rn rm))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

addi - add

machines: base

syntax: add.l $rd6,$rn6,$simm11

format:

31 30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-25-2	f-rd6	f-rn6	f-sdisp11	f-opc-6-3	f-opc
0x0	rd6	rn6	simm11	0x1	0xb

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (add-cflag SI rn6 simm11 0))
      (set vbit (add-oflag SI rn6 simm11 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd6 (add SI rn6 simm11))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

addi16 - add

machines: base

syntax: add.s $rd,$rn,$simm3

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-sdisp3 f-opc-6-3 f-opc

rd rn simm3 0x1 0x3

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (add-cflag SI rn simm3 0))
      (set vbit (add-oflag SI rn simm3 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd (add SI rn simm3))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

and - and

machines: base

syntax: and $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x5	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (and SI rn6 rm6))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

and16 - and

machines: base

syntax: and $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x5 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (and SI rn rm))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

asr - asr

machines: base

syntax: asr $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x6	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (sra SI rn6 (and SI rm6 31)))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

asr16 - asr

machines: base

syntax: asr $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x6 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (sra SI rn (and SI rm 31)))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

asri16 - asr

machines: base

syntax: asr $rd,$rn,$shift

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-shift f-opc-4-1 f-opc

rd rn shift 0x0 0xe

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (sra SI rn shift))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

asri32 - asr

machines: base

syntax: asr $rd6,$rn6,$shift

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9 8 7 6 5	4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-shift	f-opc-4-1	f-opc
0x0	0xe	rd6	rn6	shift	0x0	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (sra SI rn6 shift))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

b - long unconditional branch

machines: base

syntax: b.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0xe 0x8

semantics:
```
(set pc simm24)
```

b16 - short unconditional branch

machines: base

syntax: b.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0xe 0x0

semantics:
```
(set pc simm8)
```

bbeq - Conditional Branch beq

machines: base

syntax: bbeq.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0xa 0x8

semantics:

(if (or BI bzbit bzbit) (set pc simm24))

bbeq16 - Conditional Branch - 16 bitbeq

machines: base

syntax: bbeq.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0xa 0x0

semantics:

(if (or BI bzbit bzbit) (set pc simm8))

bblt - Conditional Branch blt

machines: base

syntax: bblt.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0xc 0x8

semantics:

(if (and BI bnbit (not BI bzbit))
    (set pc simm24))

bblt16 - Conditional Branch - 16 bitblt

machines: base

syntax: bblt.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0xc 0x0

semantics:

(if (and BI bnbit (not BI bzbit)) (set pc simm8))

bblte - Conditional Branch blte

machines: base

syntax: bblte.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0xd 0x8

semantics:

(if (or BI bnbit bzbit) (set pc simm24))

bblte16 - Conditional Branch - 16 bitblte

machines: base

syntax: bblte.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0xd 0x0

semantics:

(if (or BI bnbit bzbit) (set pc simm8))

bbne - Conditional Branch bne

machines: base

syntax: bbne.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0xb 0x8

semantics:
```
(if (not BI bzbit) (set pc simm24))
```

bbne16 - Conditional Branch - 16 bitbne

machines: base

syntax: bbne.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0xb 0x0

semantics:
```
(if (not BI bzbit) (set pc simm8))
```

beq - Conditional Branch eq

machines: base

syntax: beq.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x0 0x8

semantics:
```
(if (eq zbit 1) (set pc simm24))
```

beq16 - Conditional Branch - 16 biteq

machines: base

syntax: beq.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x0 0x0

semantics:
```
(if (eq zbit 1) (set pc simm8))
```

bgt - Conditional Branch gt

machines: base

syntax: bgt.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x6 0x8

semantics:

(if (and BI (not BI zbit) (eq vbit nbit))
    (set pc simm24))

bgt16 - Conditional Branch - 16 bitgt

machines: base

syntax: bgt.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x6 0x0

semantics:

(if (and BI (not BI zbit) (eq vbit nbit))
    (set pc simm8))

bgte - Conditional Branch gte

machines: base

syntax: bgte.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x7 0x8

semantics:
```
(if (eq vbit nbit) (set pc simm24))
```

bgte16 - Conditional Branch - 16 bitgte

machines: base

syntax: bgte.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x7 0x0

semantics:
```
(if (eq vbit nbit) (set pc simm8))
```

bgteu - Conditional Branch gteu

machines: base

syntax: bgteu.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x3 0x8

semantics:
```
(if (eq cbit 1) (set pc simm24))
```

bgteu16 - Conditional Branch - 16 bitgteu

machines: base

syntax: bgteu.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x3 0x0

semantics:
```
(if (eq cbit 1) (set pc simm8))
```

bgtu - Conditional Branch gtu

machines: base

syntax: bgtu.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x2 0x8

semantics:

(if (and BI cbit (not BI zbit)) (set pc simm24))

bgtu16 - Conditional Branch - 16 bitgtu

machines: base

syntax: bgtu.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x2 0x0

semantics:

(if (and BI cbit (not BI zbit)) (set pc simm8))

bitr - bit reverse

machines: base

syntax: bitr $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9 8 7 6 5	4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-shift	f-opc-4-1	f-opc
0x0	0xe	rd6	rn6	0x0	0x1	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((SI v))
      (set v rn6)
      (set v
           (or SI
               (and SI (srl SI v 1) 1431655765)
               (sll SI (and SI v 1431655765) 1)))
      (set v
           (or SI
               (and SI (srl SI v 2) 858993459)
               (sll SI (and SI v 858993459) 2)))
      (set v
           (or SI
               (and SI (srl SI v 4) 252645135)
               (sll SI (and SI v 252645135) 4)))
      (set v
           (or SI
               (and SI (srl SI v 8) 16711935)
               (sll SI (and SI v 16711935) 8)))
      (set v (or SI (srl SI v 16) (sll SI v 16)))
      (set rd6 v))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0))
    (set cbit 0)
    (set vbit 0))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

bitr16 - bit reverse short

machines: base

syntax: bitr $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-shift f-opc-4-1 f-opc

rd rn 0x0 0x1 0xe

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((SI v))
      (set v rn)
      (set v
           (or SI
               (and SI (srl SI v 1) 1431655765)
               (sll SI (and SI v 1431655765) 1)))
      (set v
           (or SI
               (and SI (srl SI v 2) 858993459)
               (sll SI (and SI v 858993459) 2)))
      (set v
           (or SI
               (and SI (srl SI v 4) 252645135)
               (sll SI (and SI v 252645135) 4)))
      (set v
           (or SI
               (and SI (srl SI v 8) 16711935)
               (sll SI (and SI v 16711935) 8)))
      (set v (or SI (srl SI v 16) (sll SI v 16)))
      (set rd v))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0))
    (set cbit 0)
    (set vbit 0))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

bkpt - breakpoint

machines: base

syntax: bkpt

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x1c 0x2

semantics:

(sequence
  ()
  (c-call VOID "epiphany_break" pc)
  (set pc pc))

bl - branch and link

machines: base

syntax: bl.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0xf 0x8

semantics:

(sequence
  ()
  (set (reg SI h-registers 14) (add USI pc 4))
  (set pc simm24))

bl16 - branch and link

machines: base

syntax: bl.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0xf 0x0

semantics:

(sequence
  ()
  (set (reg SI h-registers 14) (add USI pc 2))
  (set pc simm8))

blt - Conditional Branch lt

machines: base

syntax: blt.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x8 0x8

semantics:

(if (xor BI vbit nbit) (set pc simm24))

blt16 - Conditional Branch - 16 bitlt

machines: base

syntax: blt.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x8 0x0

semantics:
```
(if (xor BI vbit nbit) (set pc simm8))
```

blte - Conditional Branch lte

machines: base

syntax: blte.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x9 0x8

semantics:

(if (or BI zbit (xor BI vbit nbit))
    (set pc simm24))

blte16 - Conditional Branch - 16 bitlte

machines: base

syntax: blte.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x9 0x0

semantics:

(if (or BI zbit (xor BI vbit nbit))
    (set pc simm8))

blteu - Conditional Branch lteu

machines: base

syntax: blteu.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x4 0x8

semantics:

(if (or BI (not BI cbit) zbit) (set pc simm24))

blteu16 - Conditional Branch - 16 bitlteu

machines: base

syntax: blteu.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x4 0x0

semantics:

(if (or BI (not BI cbit) zbit) (set pc simm8))

bltu - Conditional Branch ltu

machines: base

syntax: bltu.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x5 0x8

semantics:
```
(if (eq cbit 0) (set pc simm24))
```

bltu16 - Conditional Branch - 16 bitltu

machines: base

syntax: bltu.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x5 0x0

semantics:
```
(if (eq cbit 0) (set pc simm8))
```

bne - Conditional Branch ne

machines: base

syntax: bne.l $simm24

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm24 f-condcode f-opc

simm24 0x1 0x8

semantics:
```
(if (eq zbit 0) (set pc simm24))
```

bne16 - Conditional Branch - 16 bitne

machines: base

syntax: bne.s $simm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-simm8 f-condcode f-opc

simm8 0x1 0x0

semantics:
```
(if (eq zbit 0) (set pc simm8))
```

cmov16B - move register B

machines: base

syntax: mov $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0xe 0x2

semantics:

(sequence
  ()
  (set rd rn)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16BEQ - move register BEQ

machines: base

syntax: movbeq $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0xa 0x2

semantics:

(sequence
  ()
  (if (or BI bzbit bzbit) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16BLT - move register BLT

machines: base

syntax: movblt $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0xc 0x2

semantics:

(sequence
  ()
  (if (and BI bnbit (not BI bzbit)) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16BLTE - move register BLTE

machines: base

syntax: movblte $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0xd 0x2

semantics:

(sequence
  ()
  (if (or BI bnbit bzbit) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16BNE - move register BNE

machines: base

syntax: movbne $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0xb 0x2

semantics:

(sequence
  ()
  (if (not BI bzbit) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16EQ - move register EQ

machines: base

syntax: moveq $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x0 0x2

semantics:

(sequence
  ()
  (if (eq zbit 1) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16GT - move register GT

machines: base

syntax: movgt $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x6 0x2

semantics:

(sequence
  ()
  (if (and BI (not BI zbit) (eq vbit nbit))
      (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16GTE - move register GTE

machines: base

syntax: movgte $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x7 0x2

semantics:

(sequence
  ()
  (if (eq vbit nbit) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16GTEU - move register GTEU

machines: base

syntax: movgteu $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x3 0x2

semantics:

(sequence
  ()
  (if (eq cbit 1) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16GTU - move register GTU

machines: base

syntax: movgtu $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x2 0x2

semantics:

(sequence
  ()
  (if (and BI cbit (not BI zbit)) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16LT - move register LT

machines: base

syntax: movlt $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x8 0x2

semantics:

(sequence
  ()
  (if (xor BI vbit nbit) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16LTE - move register LTE

machines: base

syntax: movlte $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x9 0x2

semantics:

(sequence
  ()
  (if (or BI zbit (xor BI vbit nbit)) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16LTEU - move register LTEU

machines: base

syntax: movlteu $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x4 0x2

semantics:

(sequence
  ()
  (if (or BI (not BI cbit) zbit) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16LTU - move register LTU

machines: base

syntax: movltu $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x5 0x2

semantics:

(sequence
  ()
  (if (eq cbit 0) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmov16NE - move register NE

machines: base

syntax: movne $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-dc-9-1 f-opc-8-1 f-condcode f-opc

rd rn 0x0 0x0 0x1 0x2

semantics:

(sequence
  ()
  (if (eq zbit 0) (set rd rn))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovB - move register B

machines: base

syntax: mov $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0xe	0xf

semantics:

(sequence
  ()
  (set rd6 rn6)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovBEQ - move register BEQ

machines: base

syntax: movbeq $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0xa	0xf

semantics:

(sequence
  ()
  (if (or BI bzbit bzbit) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovBLT - move register BLT

machines: base

syntax: movblt $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0xc	0xf

semantics:

(sequence
  ()
  (if (and BI bnbit (not BI bzbit)) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovBLTE - move register BLTE

machines: base

syntax: movblte $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0xd	0xf

semantics:

(sequence
  ()
  (if (or BI bnbit bzbit) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovBNE - move register BNE

machines: base

syntax: movbne $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0xb	0xf

semantics:

(sequence
  ()
  (if (not BI bzbit) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovEQ - move register EQ

machines: base

syntax: moveq $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x0	0xf

semantics:

(sequence
  ()
  (if (eq zbit 1) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovGT - move register GT

machines: base

syntax: movgt $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x6	0xf

semantics:

(sequence
  ()
  (if (and BI (not BI zbit) (eq vbit nbit))
      (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovGTE - move register GTE

machines: base

syntax: movgte $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x7	0xf

semantics:

(sequence
  ()
  (if (eq vbit nbit) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovGTEU - move register GTEU

machines: base

syntax: movgteu $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x3	0xf

semantics:

(sequence
  ()
  (if (eq cbit 1) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovGTU - move register GTU

machines: base

syntax: movgtu $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x2	0xf

semantics:

(sequence
  ()
  (if (and BI cbit (not BI zbit)) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovLT - move register LT

machines: base

syntax: movlt $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x8	0xf

semantics:

(sequence
  ()
  (if (xor BI vbit nbit) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovLTE - move register LTE

machines: base

syntax: movlte $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x9	0xf

semantics:

(sequence
  ()
  (if (or BI zbit (xor BI vbit nbit))
      (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovLTEU - move register LTEU

machines: base

syntax: movlteu $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x4	0xf

semantics:

(sequence
  ()
  (if (or BI (not BI cbit) zbit) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovLTU - move register LTU

machines: base

syntax: movltu $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x5	0xf

semantics:

(sequence
  ()
  (if (eq cbit 0) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

cmovNE - move register NE

machines: base

syntax: movne $rd6,$rn6

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-dc-9-1	f-opc-8-1	f-condcode	f-opc
0x0	0x2	rd6	rn6	0x0	0x0	0x1	0xf

semantics:

(sequence
  ()
  (if (eq zbit 0) (set rd6 rn6))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

eor - eor

machines: base

syntax: eor $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x0	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (xor SI rn6 rm6))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

eor16 - eor

machines: base

syntax: eor $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x0 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (xor SI rn rm))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_absf16 - f_abs

machines: base

syntax: fabs rd,rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rn f-opc-6-3 f-opc

rd rn rn 0x7 0x7

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp) (SI sdtmp))
    (set sdtmp (c-call SI "epiphany_fabs" rd rn rn))
    (set bnbit 0)
    (set bzbit (eq sdtmp 0))
    (set bvsbit (or BI bvsbit bvbit))
    (set busbit (or BI busbit bubit))
    (set bisbit (or BI bisbit bibit))
    (set rd sdtmp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_absf32 - f_abs

machines: base

syntax: fabs $rd6,$rn6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rn6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rn6	0x7	0xf

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp) (SI sdtmp))
    (set sdtmp
         (c-call SI "epiphany_fabs" rd6 rn6 rn6))
    (set bnbit 0)
    (set bzbit (eq sdtmp 0))
    (set bvsbit (or BI bvsbit bvbit))
    (set busbit (or BI busbit bubit))
    (set bisbit (or BI bisbit bibit))
    (set rd6 sdtmp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_addf16 - f_add

machines: base

syntax: fadd $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x0 0x7

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp (c-call SI "epiphany_fadd" rd rn rm))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp (c-call SI "epiphany_iadd" rd rn rm))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_addf32 - f_add

machines: base

syntax: fadd $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rm6	0x0	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_fadd" rd6 rn6 rm6))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd6 sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_iadd" rd6 rn6 rm6))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd6 sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_ixf16 - f_ix

machines: base

syntax: fix $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rn f-opc-6-3 f-opc

rd rn rn 0x6 0x7

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp) (SI sdtmp))
    (set sdtmp (c-call SI "epiphany_fix" rd rn rn))
    (set bzbit (eq sdtmp 0))
    (set bnbit (lt sdtmp 0))
    (set bvbit
         (c-call BI "get_epiphany_foverflowflag" sdtmp))
    (set bubit
         (c-call BI "get_epiphany_funderflowflag" sdtmp))
    (set bibit
         (c-call BI "get_epiphany_finvalidflag" sdtmp))
    (set bvsbit (or BI bvsbit bvbit))
    (set busbit (or BI busbit bubit))
    (set bisbit (or BI bisbit bibit))
    (set rd6 sdtmp)
    (if (or BI
            (and BI invExcEnbit bisbit)
            (or BI
                (and BI ovfExcEnbit busbit)
                (and BI unExcEnbit bvsbit)))
        (sequence
          ()
          (set expcause0bit 1)
          (set expcause1bit 1)
          (if (eq gidisablebit 0)
              (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                  (sequence
                    ()
                    (set kmbit 1)
                    (set gidisablebit 1)
                    (set (reg USI h-core-registers 8) (add USI pc 2))
                    (set (reg USI h-core-registers 13)
                         (or USI (reg USI h-core-registers 13) 2))
                    (set pc 4))
                  (set (reg USI h-core-registers 10)
                       (or USI (reg USI h-core-registers 10) 2))))))
    (set rd sdtmp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_ixf32 - f_ix

machines: base

syntax: fix $rd6,$rn6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rn6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rn6	0x6	0xf

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp) (SI sdtmp))
    (set sdtmp
         (c-call SI "epiphany_fix" rd6 rn6 rm6))
    (set bzbit (eq sdtmp 0))
    (set bnbit (lt sdtmp 0))
    (set bvbit
         (c-call BI "get_epiphany_foverflowflag" sdtmp))
    (set bubit
         (c-call BI "get_epiphany_funderflowflag" sdtmp))
    (set bibit
         (c-call BI "get_epiphany_finvalidflag" sdtmp))
    (set bvsbit (or BI bvsbit bvbit))
    (set busbit (or BI busbit bubit))
    (set bisbit (or BI bisbit bibit))
    (set rd6 sdtmp)
    (if (or BI
            (and BI invExcEnbit bisbit)
            (or BI
                (and BI ovfExcEnbit busbit)
                (and BI unExcEnbit bvsbit)))
        (sequence
          ()
          (set expcause0bit 1)
          (set expcause1bit 1)
          (if (eq gidisablebit 0)
              (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                  (sequence
                    ()
                    (set kmbit 1)
                    (set gidisablebit 1)
                    (set (reg USI h-core-registers 8) (add USI pc 2))
                    (set (reg USI h-core-registers 13)
                         (or USI (reg USI h-core-registers 13) 2))
                    (set pc 4))
                  (set (reg USI h-core-registers 10)
                       (or USI (reg USI h-core-registers 10) 2)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_loatf16 - f_loat

machines: base

syntax: float $rd,$rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rn f-opc-6-3 f-opc

frd frn frn 0x5 0x7

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp) (SI sdtmp))
    (set sdtmp (c-call SI "epiphany_float" rd rn rn))
    (set bnbit (lt sdtmp 0))
    (set bzbit (eq sdtmp 0))
    (set bvsbit (or BI bvsbit bvbit))
    (set busbit (or BI busbit bubit))
    (set bisbit (or BI bisbit bibit))
    (set rd sdtmp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_loatf32 - f_loat

machines: base

syntax: float $rd6,$rn6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rn6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rn6	0x5	0xf

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp) (SI sdtmp))
    (set sdtmp
         (c-call SI "epiphany_float" rd6 rn6 rn6))
    (set bnbit (lt sdtmp 0))
    (set bzbit (eq sdtmp 0))
    (set bvsbit (or BI bvsbit bvbit))
    (set busbit (or BI busbit bubit))
    (set bisbit (or BI bisbit bibit))
    (set rd6 sdtmp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_maddf16 - f_madd

machines: base

syntax: fmadd $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x3 0x7

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp (c-call SI "epiphany_fmadd" rd rn rm))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp (c-call SI "epiphany_imadd" rd rn rm))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_maddf32 - f_madd

machines: base

syntax: fmadd $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rm6	0x3	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_fmadd" rd6 rn6 rm6))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd6 sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_imadd" rd6 rn6 rm6))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd6 sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_msubf16 - f_msub

machines: base

syntax: fmsub $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x4 0x7

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp (c-call SI "epiphany_fmsub" rd rn rm))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp (c-call SI "epiphany_imsub" rd rn rm))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_msubf32 - f_msub

machines: base

syntax: fmsub $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rm6	0x4	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_fmsub" rd6 rn6 rm6))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd6 sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_imsub" rd6 rn6 rm6))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd6 sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_mulf16 - f_mul

machines: base

syntax: fmul $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x2 0x7

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp (c-call SI "epiphany_fmul" rd rn rm))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp (c-call SI "epiphany_imul" rd rn rm))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_mulf32 - f_mul

machines: base

syntax: fmul $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rm6	0x2	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_fmul" rd6 rn6 rm6))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd6 sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_imul" rd6 rn6 rm6))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd6 sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_recipf32 - f_recip

machines: base

syntax: frecip $frd6,$frn6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-2	f-dc-20-1	f-opc-19-4	f-rd6	f-rn6	f-rn6	f-opc-6-3	f-opc
0x0	0x1	0x7	frd6	frn6	frn6	0x0	0xf

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp))
    (set bvbit 0)
    (set busbit 0)
    (set fptemp (c-call SF "epiphany_frecip" frn6))
    (set bnbit (lt fptemp 0))
    (set bzbit (eq fptemp 0))
    (set bvsbit (or BI bvsbit bvbit))
    (set frd6 fptemp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_sqrtf32 - f_sqrt

machines: base

syntax: fsqrt $frd6,$frn6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-2	f-dc-20-1	f-opc-19-4	f-rd6	f-rn6	f-rn6	f-opc-6-3	f-opc
0x0	0x1	0x7	frd6	frn6	frn6	0x1	0xf

semantics:

(sequence
  ()
  (sequence
    ((SF fptemp))
    (set bvbit 0)
    (set busbit 0)
    (set fptemp (c-call SF "epiphany_fsqrt" frn6))
    (set bnbit (lt fptemp 0))
    (set bzbit (eq fptemp 0))
    (set bvsbit (or BI bvsbit bvbit))
    (set frd6 fptemp))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_subf16 - f_sub

machines: base

syntax: fsub $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x1 0x7

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp (c-call SI "epiphany_fsub" rd rn rm))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp (c-call SI "epiphany_isub" rd rn rm))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

f_subf32 - f_sub

machines: base

syntax: fsub $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x7	rd6	rn6	rm6	0x1	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (if (eq arithmetic-modebit2 0)
        (sequence
          ((SF fptemp) (SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_fsub" rd6 rn6 rm6))
          (set bzbit
               (c-call BI "get_epiphany_fzeroflag" sdtmp))
          (set bnbit
               (c-call BI "get_epiphany_fnegativeflag" sdtmp))
          (set bvbit
               (c-call BI "get_epiphany_foverflowflag" sdtmp))
          (set bubit
               (c-call BI "get_epiphany_funderflowflag" sdtmp))
          (set bibit
               (c-call BI "get_epiphany_finvalidflag" sdtmp))
          (set bvsbit (or BI bvsbit bvbit))
          (set busbit (or BI busbit bubit))
          (set bisbit (or BI bisbit bibit))
          (set rd6 sdtmp)
          (if (or BI
                  (and BI invExcEnbit bisbit)
                  (or BI
                      (and BI ovfExcEnbit bvsbit)
                      (and BI unExcEnbit busbit)))
              (sequence
                ()
                (set expcause0bit 1)
                (set expcause1bit 1)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))))
    (if (eq arithmetic-modebit2 1)
        (sequence
          ((SI sdtmp))
          (set sdtmp
               (c-call SI "epiphany_isub" rd6 rn6 rm6))
          (set bzbit (eq sdtmp 0))
          (set bnbit (lt sdtmp 0))
          (set rd6 sdtmp))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

fdep - fdep

machines: base

syntax: fdep $rd6,$rn6,$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-2	f-dc-20-1	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x1	0xa	rd6	rn6	rm6	0x1	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

fext - fext

machines: base

syntax: fext $rd6,$rn6,$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-2	f-dc-20-1	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x1	0xa	rd6	rn6	rm6	0x0	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

gidis - global interrupt disable

machines: base

syntax: gid

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-6 f-gien-gidis-9-1 f-opc-8-5 f-opc

0x0 0x1 0x19 0x2

semantics:

(sequence
  ()
  (set gidisablebit 1)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

gien - global interrupt enable

machines: base

syntax: gie

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-6 f-gien-gidis-9-1 f-opc-8-5 f-opc

0x0 0x0 0x19 0x2

semantics:

(sequence
  ()
  (set gidisablebit 0)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

idle - idle until interrupt

machines: base

syntax: idle

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x1b 0x2

semantics:

(sequence
  ()
  (set caibit 0)
  (c-code
    VOID
    "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, 		pc, sim_exited, 0);"))

jalr - jump and link register

machines: base

syntax: jalr $rn6

format:

31 30 29	28 27 26 25 24 23	22 21 20 19	18 17 16	15 14 13 12 11 10	9	8 7 6 5 4	3 2 1 0
f-dc-31-3	f-dc-25-6	f-opc-19-4	f-dc-15-3	f-rn6	f-dc-9-1	f-opc-8-5	f-opc
0x0	0x0	0x2	0x0	rn6	0x0	0x15	0xf

semantics:

(sequence
  ()
  (set (reg SI h-registers 14) (add USI pc 4))
  (set pc rn6))

jalr16 - jump and link register

machines: base

syntax: jalr $rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-3 f-rn f-dc-9-1 f-opc-8-5 f-opc

0x0 rn 0x0 0x15 0x2

semantics:

(sequence
  ()
  (set (reg SI h-registers 14) (add USI pc 2))
  (set pc rn))

jr - unconditional jump

machines: base

syntax: jr $rn6

format:

31 30 29	28 27 26 25 24 23	22 21 20 19	18 17 16	15 14 13 12 11 10	9	8 7 6 5 4	3 2 1 0
f-dc-31-3	f-dc-25-6	f-opc-19-4	f-dc-15-3	f-rn6	f-dc-9-1	f-opc-8-5	f-opc
0x0	0x0	0x2	0x0	rn6	0x0	0x14	0xf

semantics:
```
(set pc rn6)
```

jr16 - unconditional jump 16

machines: base

syntax: jr $rn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-3 f-rn f-dc-9-1 f-opc-8-5 f-opc

0x0 rn 0x0 0x14 0x2

semantics:
```
(set pc rn)
```

ldrbd.l - load QI displacement

machines: base

syntax: ldrb $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x0	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_BYTE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set rd6 (zext SI (mem QI effa)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrbd16.s - load QI displacement

machines: base

syntax: ldrb $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x0 0x0 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_BYTE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set rd (zext SI (mem QI effa)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrbdpm.l - load QI displacement post-modify

machines: base

syntax: ldrb $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x0	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_BYTE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set rd6 (zext SI (mem QI rn6))))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrbp.l - load QI postmodify

machines: base

syntax: ldrb $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x0	0x0	0xd

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm6)
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set rd6 (zext SI (mem QI rn6))))))
    (if f-addsubx
        (set rn6 (sub SI rn6 tmprm))
        (set rn6 (add SI rn6 tmprm))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrbp16.s - load QI postmodify

machines: base

syntax: ldrb $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x0 0x0 0x5

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm)
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI rn 0) 0))
                   ((OPW_SHORT) (eq (and SI rn 1) 0))
                   ((OPW_WORD) (eq (and SI rn 3) 0))
                   (else (eq (and SI rn 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn)
            (set rd (zext SI (mem QI rn))))))
    (set rn (add SI rn tmprm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrbx.l - load QI indexed

machines: base

syntax: ldrb $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x0	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_BYTE)
                       ((OPW_BYTE) (eq (and SI (sub SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (sub SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (sub SI rn6 rm6) 3) 0))
                       (else (eq (and SI (sub SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (sub SI rn6 rm6))
                (set rd6 (zext SI (mem QI (sub SI rn6 rm6)))))))
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_BYTE)
                       ((OPW_BYTE) (eq (and SI (add SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (add SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (add SI rn6 rm6) 3) 0))
                       (else (eq (and SI (add SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (add SI rn6 rm6))
                (set rd6 (zext SI (mem QI (add SI rn6 rm6)))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrbx16.s - load QI indexed

machines: base

syntax: ldrb $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x0 0x0 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI (add SI rn rm) 0) 0))
                   ((OPW_SHORT) (eq (and SI (add SI rn rm) 1) 0))
                   ((OPW_WORD) (eq (and SI (add SI rn rm) 3) 0))
                   (else (eq (and SI (add SI rn rm) 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr (add SI rn rm))
            (set rd (zext SI (mem QI (add SI rn rm))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrd.l - load SI displacement

machines: base

syntax: ldr $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x2	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_WORD)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set rd6 (zext SI (mem SI effa)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrd16.s - load SI displacement

machines: base

syntax: ldr $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x2 0x0 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_WORD)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set rd (zext SI (mem SI effa)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdd.l - load DI displacement

machines: base

syntax: ldrd $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x3	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_DOUBLE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((SI loadaddr) (BI isAligmentAccess))
      (set loadaddr effa)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                   ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                   (else (eq (and SI loadaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr loadaddr)
            (set rd6 (mem SI loadaddr))
            (set loadaddr (add SI loadaddr 4))
            (set memaddr loadaddr)
            (set (reg SI h-registers (add INT (index-of rd6) 1))
                 (mem SI loadaddr))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdd16.s - load DI displacement

machines: base

syntax: ldrd $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x3 0x0 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_DOUBLE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((SI loadaddr) (BI isAligmentAccess))
      (set loadaddr effa)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                   ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                   (else (eq (and SI loadaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr loadaddr)
            (set rd (mem SI loadaddr))
            (set loadaddr (add SI loadaddr 4))
            (set memaddr loadaddr)
            (set (reg SI h-registers (add INT (index-of rd) 1))
                 (mem SI loadaddr))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrddpm.l - load DI displacement post-modify

machines: base

syntax: ldrd $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x3	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_DOUBLE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((SI loadaddr) (BI isAligmentAccess))
      (set loadaddr rn6)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                   ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                   (else (eq (and SI loadaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr loadaddr)
            (set rd6 (mem SI loadaddr))
            (set loadaddr (add SI loadaddr 4))
            (set memaddr loadaddr)
            (set (reg SI h-registers (add INT (index-of rd6) 1))
                 (mem SI loadaddr)))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdp.l - load DI postmodify

machines: base

syntax: ldrd $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x3	0x0	0xd

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm6)
    (sequence
      ((SI loadaddr) (BI isAligmentAccess))
      (set loadaddr rn6)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                   ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                   (else (eq (and SI loadaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr loadaddr)
            (set rd6 (mem SI loadaddr))
            (set loadaddr (add SI loadaddr 4))
            (set memaddr loadaddr)
            (set (reg SI h-registers (add INT (index-of rd6) 1))
                 (mem SI loadaddr)))))
    (if f-addsubx
        (set rn6 (sub SI rn6 tmprm))
        (set rn6 (add SI rn6 tmprm))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdp16.s - load DI postmodify

machines: base

syntax: ldrd $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x3 0x0 0x5

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm)
    (sequence
      ((SI loadaddr) (BI isAligmentAccess))
      (set loadaddr rn)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                   ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                   (else (eq (and SI loadaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr loadaddr)
            (set rd (mem SI loadaddr))
            (set loadaddr (add SI loadaddr 4))
            (set memaddr loadaddr)
            (set (reg SI h-registers (add INT (index-of rd) 1))
                 (mem SI loadaddr)))))
    (set rn (add SI rn tmprm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdpm.l - load SI displacement post-modify

machines: base

syntax: ldr $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x2	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_WORD)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set rd6 (zext SI (mem SI rn6))))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdx.l - load DI indexed

machines: base

syntax: ldrd $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x3	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((SI loadaddr) (BI isAligmentAccess))
          (set loadaddr (sub SI rn6 rm6))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_DOUBLE)
                       ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                       ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                       ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                       (else (eq (and SI loadaddr 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr loadaddr)
                (set rd6 (mem SI loadaddr))
                (set loadaddr (add SI loadaddr 4))
                (set memaddr loadaddr)
                (set (reg SI h-registers (add INT (index-of rd6) 1))
                     (mem SI loadaddr)))))
        (sequence
          ((SI loadaddr) (BI isAligmentAccess))
          (set loadaddr (add SI rn6 rm6))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_DOUBLE)
                       ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                       ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                       ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                       (else (eq (and SI loadaddr 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr loadaddr)
                (set rd6 (mem SI loadaddr))
                (set loadaddr (add SI loadaddr 4))
                (set memaddr loadaddr)
                (set (reg SI h-registers (add INT (index-of rd6) 1))
                     (mem SI loadaddr)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrdx16.s - load DI indexed

machines: base

syntax: ldrd $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x3 0x0 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((SI loadaddr) (BI isAligmentAccess))
      (set loadaddr (add SI rn rm))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI loadaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI loadaddr 1) 0))
                   ((OPW_WORD) (eq (and SI loadaddr 3) 0))
                   (else (eq (and SI loadaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr loadaddr)
            (set rd (mem SI loadaddr))
            (set loadaddr (add SI loadaddr 4))
            (set memaddr loadaddr)
            (set (reg SI h-registers (add INT (index-of rd) 1))
                 (mem SI loadaddr))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhd.l - load HI displacement

machines: base

syntax: ldrh $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x1	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_SHORT)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set rd6 (zext SI (mem HI effa)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhd16.s - load HI displacement

machines: base

syntax: ldrh $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x1 0x0 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_SHORT)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set rd (zext SI (mem HI effa)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhdpm.l - load HI displacement post-modify

machines: base

syntax: ldrh $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x1	0x0	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_SHORT)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set rd6 (zext SI (mem HI rn6))))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhp.l - load HI postmodify

machines: base

syntax: ldrh $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x1	0x0	0xd

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm6)
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set rd6 (zext SI (mem HI rn6))))))
    (if f-addsubx
        (set rn6 (sub SI rn6 tmprm))
        (set rn6 (add SI rn6 tmprm))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhp16.s - load HI postmodify

machines: base

syntax: ldrh $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x1 0x0 0x5

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm)
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI rn 0) 0))
                   ((OPW_SHORT) (eq (and SI rn 1) 0))
                   ((OPW_WORD) (eq (and SI rn 3) 0))
                   (else (eq (and SI rn 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn)
            (set rd (zext SI (mem HI rn))))))
    (set rn (add SI rn tmprm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhx.l - load HI indexed

machines: base

syntax: ldrh $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x1	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_SHORT)
                       ((OPW_BYTE) (eq (and SI (sub SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (sub SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (sub SI rn6 rm6) 3) 0))
                       (else (eq (and SI (sub SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (sub SI rn6 rm6))
                (set rd6 (zext SI (mem HI (sub SI rn6 rm6)))))))
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_SHORT)
                       ((OPW_BYTE) (eq (and SI (add SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (add SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (add SI rn6 rm6) 3) 0))
                       (else (eq (and SI (add SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (add SI rn6 rm6))
                (set rd6 (zext SI (mem HI (add SI rn6 rm6)))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrhx16.s - load HI indexed

machines: base

syntax: ldrh $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x1 0x0 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI (add SI rn rm) 0) 0))
                   ((OPW_SHORT) (eq (and SI (add SI rn rm) 1) 0))
                   ((OPW_WORD) (eq (and SI (add SI rn rm) 3) 0))
                   (else (eq (and SI (add SI rn rm) 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr (add SI rn rm))
            (set rd (zext SI (mem HI (add SI rn rm))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrp.l - load SI postmodify

machines: base

syntax: ldr $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x2	0x0	0xd

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm6)
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set rd6 (zext SI (mem SI rn6))))))
    (if f-addsubx
        (set rn6 (sub SI rn6 tmprm))
        (set rn6 (add SI rn6 tmprm))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrp16.s - load SI postmodify

machines: base

syntax: ldr $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x2 0x0 0x5

semantics:

(sequence
  ()
  (sequence
    ((SI tmprm))
    (set tmprm rm)
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI rn 0) 0))
                   ((OPW_SHORT) (eq (and SI rn 1) 0))
                   ((OPW_WORD) (eq (and SI rn 3) 0))
                   (else (eq (and SI rn 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn)
            (set rd (zext SI (mem SI rn))))))
    (set rn (add SI rn tmprm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrx.l - load SI indexed

machines: base

syntax: ldr $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x2	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_WORD)
                       ((OPW_BYTE) (eq (and SI (sub SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (sub SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (sub SI rn6 rm6) 3) 0))
                       (else (eq (and SI (sub SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (sub SI rn6 rm6))
                (set rd6 (zext SI (mem SI (sub SI rn6 rm6)))))))
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_WORD)
                       ((OPW_BYTE) (eq (and SI (add SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (add SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (add SI rn6 rm6) 3) 0))
                       (else (eq (and SI (add SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (add SI rn6 rm6))
                (set rd6 (zext SI (mem SI (add SI rn6 rm6)))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

ldrx16.s - load SI indexed

machines: base

syntax: ldr $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x2 0x0 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI (add SI rn rm) 0) 0))
                   ((OPW_SHORT) (eq (and SI (add SI rn rm) 1) 0))
                   ((OPW_WORD) (eq (and SI (add SI rn rm) 3) 0))
                   (else (eq (and SI (add SI rn rm) 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr (add SI rn rm))
            (set rd (zext SI (mem SI (add SI rn rm))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lfsr - lfsr

machines: base

syntax: lfsr $rd6,$rn6,$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-2	f-dc-20-1	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0x1	0xa	rd6	rn6	rm6	0x2	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsl - lsl

machines: base

syntax: lsl $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x2	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (sll SI rn6 (and SI rm6 31)))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsl16 - lsl

machines: base

syntax: lsl $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x2 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (sll SI rn (and SI rm 31)))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsli16 - lsl

machines: base

syntax: lsl $rd,$rn,$shift

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-shift f-opc-4-1 f-opc

rd rn shift 0x1 0x6

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (sll SI rn shift))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsli32 - lsl

machines: base

syntax: lsl $rd6,$rn6,$shift

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9 8 7 6 5	4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-shift	f-opc-4-1	f-opc
0x0	0x6	rd6	rn6	shift	0x1	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (sll SI rn6 shift))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsr - lsr

machines: base

syntax: lsr $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x4	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (srl SI rn6 (and SI rm6 31)))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsr16 - lsr

machines: base

syntax: lsr $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x4 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (srl SI rn (and SI rm 31)))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsri16 - lsr

machines: base

syntax: lsr $rd,$rn,$shift

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-shift f-opc-4-1 f-opc

rd rn shift 0x0 0x6

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (srl SI rn shift))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

lsri32 - lsr

machines: base

syntax: lsr $rd6,$rn6,$shift

format:

31 30 29 28 27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9 8 7 6 5	4	3 2 1 0
f-dc-25-6	f-opc-19-4	f-rd6	f-rn6	f-shift	f-opc-4-1	f-opc
0x0	0x6	rd6	rn6	shift	0x0	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (srl SI rn6 shift))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

mbkpt - multicorebreakpoint

machines: base

syntax: mbkpt

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x1 0x1c 0x2

semantics:
```
(nop)
```

mov16 - mov imm16

machines: base

syntax: mov.l $rd6,$imm16

format:

31	30 29 28 27	26 25 24 23 22 21	20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5	4	3 2 1 0
f-dc-28-1	f-opc-19-4	f-rd6	f-imm16	f-opc-4-1	f-opc
0x0	0x2	rd6	imm16	0x0	0xb

semantics:

(sequence
  ()
  (set rd6 (zext SI imm16))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

mov8 - mov imm8

machines: base

syntax: mov.b $rd,$imm8

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-imm8 f-opc-4-1 f-opc

rd imm8 0x0 0x3

semantics:

(sequence
  ()
  (set rd (zext SI imm8))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movfs16 - move from special register

machines: base

syntax: movfs $rd,$sn

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-sn f-dc-9-1 f-opc-8-5 f-opc

rd sn 0x0 0x11 0x2

semantics:

(sequence
  ()
  (set rd sn)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movfs6 - move from 6

machines: base

syntax: movfs $rd6,$sn6

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x0	0x2	rd6	sn6	0x0	0x1	0x1	0xf

semantics:

(sequence
  ()
  (set rd6 sn6)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movfsdma - move from dma

machines: base

syntax: movfs $rd6,$sndma

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x1	0x2	rd6	sndma	0x0	0x1	0x1	0xf

semantics:

(sequence
  ()
  (set rd6 sndma)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movfsmem - move from mem

machines: base

syntax: movfs $rd6,$snmem

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x2	0x2	rd6	snmem	0x0	0x1	0x1	0xf

semantics:

(sequence
  ()
  (set rd6 snmem)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movfsmesh - move from mesh

machines: base

syntax: movfs $rd6,$snmesh

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x3	0x2	rd6	snmesh	0x0	0x1	0x1	0xf

semantics:

(sequence
  ()
  (set rd6 snmesh)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movt - movt imm16

machines: base

syntax: movt $rd6,$imm16

format:

31	30 29 28 27	26 25 24 23 22 21	20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5	4	3 2 1 0
f-dc-28-1	f-opc-19-4	f-rd6	f-imm16	f-opc-4-1	f-opc
0x1	0x2	rd6	imm16	0x0	0xb

semantics:

(sequence
  ()
  (set rd6
       (or SI (and SI rd6 65535) (sll SI imm16 16)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movts16 - move to special reg

machines: base

syntax: movts $sn,$rd

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-sn f-dc-9-1 f-opc-8-5 f-opc

rd sn 0x0 0x10 0x2

semantics:

(sequence
  ()
  (set sn rd)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movts6 - move to 6

machines: base

syntax: movts $sn6,$rd6

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x0	0x2	rd6	sn6	0x0	0x1	0x0	0xf

semantics:

(sequence
  ()
  (set sn6 rd6)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movtsdma - move to dma

machines: base

syntax: movts $sndma,$rd6

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x1	0x2	rd6	sndma	0x0	0x1	0x0	0xf

semantics:

(sequence
  ()
  (set sndma rd6)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movtsmem - move to mem

machines: base

syntax: movts $snmem,$rd6

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x2	0x2	rd6	snmem	0x0	0x1	0x0	0xf

semantics:

(sequence
  ()
  (set snmem rd6)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

movtsmesh - move to mesh

machines: base

syntax: movts $snmesh,$rd6

format:

31 30 29 28	27 26	25 24 23 22	21 20 19 18 17 16	15 14 13 12 11 10	9	8	7 6 5 4	3 2 1 0
f-dc-25-4	f-dc-21-2	f-opc-19-4	f-rd6	f-sn6	f-dc-9-1	f-opc-8-1	f-dc-7-4	f-opc
0x0	0x3	0x2	rd6	snmesh	0x0	0x1	0x0	0xf

semantics:

(sequence
  ()
  (set snmesh rd6)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

nop - no-operation

machines: base

syntax: nop

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x1a 0x2

semantics:

(sequence
  ()
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

orr - orr

machines: base

syntax: orr $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x7	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd6 (or SI rn6 rm6))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

orr16 - orr

machines: base

syntax: orr $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x7 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence () (set cbit 0) (set vbit 0))
    (set rd (or SI rn rm))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

rti - return from interrupt

machines: base

syntax: rti

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x1d 0x2

semantics:

(sequence
  ()
  (set (reg USI h-core-registers 13)
       (c-call
         SI
         "epiphany_rti"
         (reg USI h-core-registers 13)
         (reg USI h-core-registers 9)))
  (set gidisablebit 0)
  (set kmbit 0)
  (set pc (reg USI h-core-registers 8)))

rts - return from subroutine

machines: base

syntax: rts

format:

31 30 29	28 27 26	25 24 23 22 21 20	19 18 17 16	15 14 13	12 11 10	9	8 7 6 5 4	3 2 1 0
f-dc-31-3	f-rn-x	f-dc-25-6	f-opc-19-4	f-dc-15-3	f-rn	f-dc-9-1	f-opc-8-5	f-opc
0x0	0x1	0x0	0x2	0x0	0x6	0x0	0x14	0xf

semantics:
```
(set pc (reg SI h-registers 14))
```

snop - no-operation

machines: base

syntax: snop

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x3a 0x2

semantics:

(sequence
  ()
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbd - store QI displacement

machines: base

syntax: strb $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x0	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_BYTE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set (mem QI effa) rd6)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbd16 - store QI displacement

machines: base

syntax: strb $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x0 0x1 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_BYTE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set (mem QI effa) rd)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbdpm - store QI displacement post-modify

machines: base

syntax: strb $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x0	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_BYTE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set (mem QI rn6) rd6))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbp - store QI postmodify

machines: base

syntax: strb $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x0	0x1	0xd

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set (mem QI rn6) rd6))))
    (if f-addsubx
        (set rn6 (sub SI rn6 rm6))
        (set rn6 (add SI rn6 rm6))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbp16 - store QI postmodify

machines: base

syntax: strb $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x0 0x1 0x5

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI rn 0) 0))
                   ((OPW_SHORT) (eq (and SI rn 1) 0))
                   ((OPW_WORD) (eq (and SI rn 3) 0))
                   (else (eq (and SI rn 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn)
            (set (mem QI rn) rd))))
    (set rn (add SI rn rm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbx - storeQI indexed

machines: base

syntax: strb $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x0	0x1	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_BYTE)
                       ((OPW_BYTE) (eq (and SI (sub SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (sub SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (sub SI rn6 rm6) 3) 0))
                       (else (eq (and SI (sub SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (sub SI rn6 rm6))
                (set (mem QI (sub SI rn6 rm6)) rd6))))
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_BYTE)
                       ((OPW_BYTE) (eq (and SI (add SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (add SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (add SI rn6 rm6) 3) 0))
                       (else (eq (and SI (add SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (add SI rn6 rm6))
                (set (mem QI (add SI rn6 rm6)) rd6))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strbx16 - storeQI indexed

machines: base

syntax: strb $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x0 0x1 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI (add SI rn rm) 0) 0))
                   ((OPW_SHORT) (eq (and SI (add SI rn rm) 1) 0))
                   ((OPW_WORD) (eq (and SI (add SI rn rm) 3) 0))
                   (else (eq (and SI (add SI rn rm) 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr (add SI rn rm))
            (set (mem QI (add SI rn rm)) rd)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strd - store SI displacement

machines: base

syntax: str $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x2	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_WORD)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set (mem SI effa) rd6)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strd16 - store SI displacement

machines: base

syntax: str $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x2 0x1 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_WORD)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set (mem SI effa) rd)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdd - store DI displacement

machines: base

syntax: strd $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x3	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_DOUBLE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((SI storeaddr) (BI isAligmentAccess))
      (set storeaddr effa)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                   ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                   (else (eq (and SI storeaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr storeaddr)
            (set (mem SI storeaddr) rd6)
            (set storeaddr (add SI storeaddr 4))
            (set memaddr storeaddr)
            (set (mem SI storeaddr)
                 (reg SI h-registers (add INT (index-of rd6) 1)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdd16 - store DI displacement

machines: base

syntax: strd $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x3 0x1 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_DOUBLE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((SI storeaddr) (BI isAligmentAccess))
      (set storeaddr effa)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                   ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                   (else (eq (and SI storeaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr storeaddr)
            (set (mem SI storeaddr) rd)
            (set storeaddr (add SI storeaddr 4))
            (set memaddr storeaddr)
            (set (mem SI storeaddr)
                 (reg SI h-registers (add INT (index-of rd) 1)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strddpm - store DI displacement post-modify

machines: base

syntax: strd $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x3	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_DOUBLE)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((SI storeaddr) (BI isAligmentAccess))
      (set storeaddr rn6)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                   ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                   (else (eq (and SI storeaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr storeaddr)
            (set (mem SI storeaddr) rd6)
            (set storeaddr (add SI storeaddr 4))
            (set memaddr storeaddr)
            (set (mem SI storeaddr)
                 (reg SI h-registers (add INT (index-of rd6) 1))))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdp - store DI postmodify

machines: base

syntax: strd $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x3	0x1	0xd

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((SI storeaddr) (BI isAligmentAccess))
      (set storeaddr rn6)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                   ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                   (else (eq (and SI storeaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr storeaddr)
            (set (mem SI storeaddr) rd6)
            (set storeaddr (add SI storeaddr 4))
            (set memaddr storeaddr)
            (set (mem SI storeaddr)
                 (reg SI h-registers (add INT (index-of rd6) 1))))))
    (if f-addsubx
        (set rn6 (sub SI rn6 rm6))
        (set rn6 (add SI rn6 rm6))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdp16 - store DI postmodify

machines: base

syntax: strd $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x3 0x1 0x5

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((SI storeaddr) (BI isAligmentAccess))
      (set storeaddr rn)
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                   ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                   (else (eq (and SI storeaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr storeaddr)
            (set (mem SI storeaddr) rd)
            (set storeaddr (add SI storeaddr 4))
            (set memaddr storeaddr)
            (set (mem SI storeaddr)
                 (reg SI h-registers (add INT (index-of rd) 1))))))
    (set rn (add SI rn rm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdpm - store SI displacement post-modify

machines: base

syntax: str $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x2	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_WORD)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set (mem SI rn6) rd6))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdx - storeDI indexed

machines: base

syntax: strd $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x3	0x1	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((SI storeaddr) (BI isAligmentAccess))
          (set storeaddr (sub SI rn6 rm6))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_DOUBLE)
                       ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                       ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                       ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                       (else (eq (and SI storeaddr 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr storeaddr)
                (set (mem SI storeaddr) rd6)
                (set storeaddr (add SI storeaddr 4))
                (set memaddr storeaddr)
                (set (mem SI storeaddr)
                     (reg SI h-registers (add INT (index-of rd6) 1))))))
        (sequence
          ((SI storeaddr) (BI isAligmentAccess))
          (set storeaddr (add SI rn6 rm6))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_DOUBLE)
                       ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                       ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                       ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                       (else (eq (and SI storeaddr 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr storeaddr)
                (set (mem SI storeaddr) rd6)
                (set storeaddr (add SI storeaddr 4))
                (set memaddr storeaddr)
                (set (mem SI storeaddr)
                     (reg SI h-registers (add INT (index-of rd6) 1))))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strdx16 - storeDI indexed

machines: base

syntax: strd $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x3 0x1 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((SI storeaddr) (BI isAligmentAccess))
      (set storeaddr (add SI rn rm))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_DOUBLE)
                   ((OPW_BYTE) (eq (and SI storeaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI storeaddr 1) 0))
                   ((OPW_WORD) (eq (and SI storeaddr 3) 0))
                   (else (eq (and SI storeaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr storeaddr)
            (set (mem SI storeaddr) rd)
            (set storeaddr (add SI storeaddr 4))
            (set memaddr storeaddr)
            (set (mem SI storeaddr)
                 (reg SI h-registers (add INT (index-of rd) 1)))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhd - store HI displacement

machines: base

syntax: strh $rd6,[$rn6,$dpmi$disp11]

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x0	dpmi	rd6	rn6	disp11	0x1	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_SHORT)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (if dpmi
        (set effa (sub SI rn6 (sll UINT disp11 scale)))
        (set effa (add SI rn6 (sll UINT disp11 scale))))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set (mem HI effa) rd6)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhd16 - store HI displacement

machines: base

syntax: strh $rd,[$rn,$disp3]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-disp3 f-wordsize f-store f-opc

rd rn disp3 0x1 0x1 0x4

semantics:

(sequence
  ()
  (sequence
    ((SI effa) (SI scale))
    (set scale
         (case SI
               (enum INT OPW_SHORT)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (set effa (add SI rn (sll UINT disp3 scale)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI effa 0) 0))
                   ((OPW_SHORT) (eq (and SI effa 1) 0))
                   ((OPW_WORD) (eq (and SI effa 3) 0))
                   (else (eq (and SI effa 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr effa)
            (set (mem HI effa) rd)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhdpm - store HI displacement post-modify

machines: base

syntax: strh $rd6,[$rn6],$dpmi$disp11

format:

31	30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5	4	3 2 1 0
f-pm	f-subd	f-rd6	f-rn6	f-disp11	f-wordsize	f-store	f-opc
0x1	dpmi	rd6	rn6	disp11	0x1	0x1	0xc

semantics:

(sequence
  ()
  (sequence
    ((SI scale))
    (set scale
         (case SI
               (enum INT OPW_SHORT)
               ((OPW_BYTE) 0)
               ((OPW_SHORT) 1)
               ((OPW_WORD) 2)
               (else 3)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set (mem HI rn6) rd6))))
    (if dpmi
        (set rn6 (sub SI rn6 (sll UINT disp11 scale)))
        (set rn6 (add SI rn6 (sll UINT disp11 scale)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhp - store HI postmodify

machines: base

syntax: strh $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x1	0x1	0xd

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set (mem HI rn6) rd6))))
    (if f-addsubx
        (set rn6 (sub SI rn6 rm6))
        (set rn6 (add SI rn6 rm6))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhp16 - store HI postmodify

machines: base

syntax: strh $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x1 0x1 0x5

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI rn 0) 0))
                   ((OPW_SHORT) (eq (and SI rn 1) 0))
                   ((OPW_WORD) (eq (and SI rn 3) 0))
                   (else (eq (and SI rn 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn)
            (set (mem HI rn) rd))))
    (set rn (add SI rn rm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhx - storeHI indexed

machines: base

syntax: strh $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x1	0x1	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_SHORT)
                       ((OPW_BYTE) (eq (and SI (sub SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (sub SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (sub SI rn6 rm6) 3) 0))
                       (else (eq (and SI (sub SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (sub SI rn6 rm6))
                (set (mem HI (sub SI rn6 rm6)) rd6))))
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_SHORT)
                       ((OPW_BYTE) (eq (and SI (add SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (add SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (add SI rn6 rm6) 3) 0))
                       (else (eq (and SI (add SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (add SI rn6 rm6))
                (set (mem HI (add SI rn6 rm6)) rd6))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strhx16 - storeHI indexed

machines: base

syntax: strh $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x1 0x1 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI (add SI rn rm) 0) 0))
                   ((OPW_SHORT) (eq (and SI (add SI rn rm) 1) 0))
                   ((OPW_WORD) (eq (and SI (add SI rn rm) 3) 0))
                   (else (eq (and SI (add SI rn rm) 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr (add SI rn rm))
            (set (mem HI (add SI rn rm)) rd)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strp - store SI postmodify

machines: base

syntax: str $rd6,[$rn6],$direction$rm6

format:

31 30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-2	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	direction	0x0	rd6	rn6	rm6	0x2	0x1	0xd

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI rn6 0) 0))
                   ((OPW_SHORT) (eq (and SI rn6 1) 0))
                   ((OPW_WORD) (eq (and SI rn6 3) 0))
                   (else (eq (and SI rn6 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn6)
            (set (mem SI rn6) rd6))))
    (if f-addsubx
        (set rn6 (sub SI rn6 rm6))
        (set rn6 (add SI rn6 rm6))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strp16 - store SI postmodify

machines: base

syntax: str $rd,[$rn],$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x2 0x1 0x5

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI rn 0) 0))
                   ((OPW_SHORT) (eq (and SI rn 1) 0))
                   ((OPW_WORD) (eq (and SI rn 3) 0))
                   (else (eq (and SI rn 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr rn)
            (set (mem SI rn) rd))))
    (set rn (add SI rn rm)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strx - storeSI indexed

machines: base

syntax: str $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x0	direction	0x0	rd6	rn6	rm6	0x2	0x1	0x9

semantics:

(sequence
  ()
  (sequence
    ()
    (if f-addsubx
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_WORD)
                       ((OPW_BYTE) (eq (and SI (sub SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (sub SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (sub SI rn6 rm6) 3) 0))
                       (else (eq (and SI (sub SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (sub SI rn6 rm6))
                (set (mem SI (sub SI rn6 rm6)) rd6))))
        (sequence
          ((BI isAligmentAccess))
          (sequence
            ((BI scale))
            (set isAligmentAccess
                 (case BI
                       (enum INT OPW_WORD)
                       ((OPW_BYTE) (eq (and SI (add SI rn6 rm6) 0) 0))
                       ((OPW_SHORT) (eq (and SI (add SI rn6 rm6) 1) 0))
                       ((OPW_WORD) (eq (and SI (add SI rn6 rm6) 3) 0))
                       (else (eq (and SI (add SI rn6 rm6) 7) 0))))
            (if (not BI isAligmentAccess)
                (if (eq gidisablebit 0)
                    (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                        (sequence
                          ()
                          (set kmbit 1)
                          (set gidisablebit 1)
                          (set (reg USI h-core-registers 8) (add USI pc 2))
                          (set (reg USI h-core-registers 13)
                               (or USI (reg USI h-core-registers 13) 2))
                          (set pc 4))
                        (set (reg USI h-core-registers 10)
                             (or USI (reg USI h-core-registers 10) 2))))))
          (if (not BI (not BI isAligmentAccess))
              (sequence
                ()
                (set memaddr (add SI rn6 rm6))
                (set (mem SI (add SI rn6 rm6)) rd6))))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

strx16 - storeSI indexed

machines: base

syntax: str $rd,[$rn,$rm]

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-wordsize f-store f-opc

rd rn rm 0x2 0x1 0x1

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI (add SI rn rm) 0) 0))
                   ((OPW_SHORT) (eq (and SI (add SI rn rm) 1) 0))
                   ((OPW_WORD) (eq (and SI (add SI rn rm) 3) 0))
                   (else (eq (and SI (add SI rn rm) 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr (add SI rn rm))
            (set (mem SI (add SI rn rm)) rd)))))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

sub - sub

machines: base

syntax: sub $rd6,$rn6,$rm6

format:

31 30 29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-22-3	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-opc-6-3	f-opc
0x0	0xa	rd6	rn6	rm6	0x3	0xf

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (not BI (sub-cflag SI rn6 rm6 0)))
      (set vbit (sub-oflag SI rn6 rm6 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd6 (sub SI rn6 rm6))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

sub16 - sub

machines: base

syntax: sub $rd,$rn,$rm

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-rm f-opc-6-3 f-opc

rd rn rm 0x3 0xa

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (not BI (sub-cflag SI rn rm 0)))
      (set vbit (sub-oflag SI rn rm 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd (sub SI rn rm))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

subi - sub

machines: base

syntax: sub.l $rd6,$rn6,$simm11

format:

31 30	29 28 27 26 25 24	23 22 21 20 19 18	17 16 15 14 13 12 11 10 9 8 7	6 5 4	3 2 1 0
f-dc-25-2	f-rd6	f-rn6	f-sdisp11	f-opc-6-3	f-opc
0x0	rd6	rn6	simm11	0x3	0xb

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (not BI (sub-cflag SI rn6 simm11 0)))
      (set vbit (sub-oflag SI rn6 simm11 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd6 (sub SI rn6 simm11))
    (set zbit (eq rd6 0))
    (set nbit (lt rd6 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

subi16 - sub

machines: base

syntax: sub.s $rd,$rn,$simm3

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-rd f-rn f-sdisp3 f-opc-6-3 f-opc

rd rn simm3 0x3 0x3

semantics:

(sequence
  ()
  (sequence
    ()
    (sequence
      ()
      (set cbit (not BI (sub-cflag SI rn simm3 0)))
      (set vbit (sub-oflag SI rn simm3 0))
      (set vsbit (or BI vsbit vbit)))
    (set rd (sub SI rn simm3))
    (set zbit (eq rd 0))
    (set nbit (lt rd 0)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

swi - software interrupt

machines: base

syntax: swi

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-6 f-trap-swi-9-1 f-opc-8-5 f-opc

0x0 0x0 0x1e 0x2

semantics:

(sequence
  ()
  (if (eq gidisablebit 0)
      (if (eq (and USI (reg USI h-core-registers 9) 128) 0)
          (sequence
            ()
            (set kmbit 1)
            (set gidisablebit 1)
            (set (reg USI h-core-registers 8) (add USI pc 2))
            (set (reg USI h-core-registers 13)
                 (or USI (reg USI h-core-registers 13) 128))
            (set pc 36))
          (set (reg USI h-core-registers 10)
               (or USI (reg USI h-core-registers 10) 128)))))

swi_num - software interrupt

machines: base

syntax: swi $swi_num

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-trap-num f-trap-swi-9-1 f-opc-8-5 f-opc

swi_num 0x0 0x1e 0x2

semantics:

(sequence
  ()
  (if (eq gidisablebit 0)
      (if (eq (and USI (reg USI h-core-registers 9) 128) 0)
          (sequence
            ()
            (set kmbit 1)
            (set gidisablebit 1)
            (set (reg USI h-core-registers 8) (add USI pc 2))
            (set (reg USI h-core-registers 13)
                 (or USI (reg USI h-core-registers 13) 128))
            (set pc 36))
          (set (reg USI h-core-registers 10)
               (or USI (reg USI h-core-registers 10) 128)))))

sync - sync

machines: base

syntax: sync

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x1f 0x2

semantics:

(sequence
  ()
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

testsetbt - testset QI indexed

machines: base

syntax: testsetb $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x1	direction	0x0	rd6	rn6	rm6	0x0	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ((SI tmemaddr) (SI tmpValReg))
    (set tmpValReg rd6)
    (if f-addsubx
        (set tmemaddr (sub SI rn6 rm6))
        (set tmemaddr (add SI rn6 rm6)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_BYTE)
                   ((OPW_BYTE) (eq (and SI tmemaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI tmemaddr 1) 0))
                   ((OPW_WORD) (eq (and SI tmemaddr 3) 0))
                   (else (eq (and SI tmemaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr tmemaddr)
            (set rd6 (zext SI (mem QI tmemaddr))))))
    (if rd6 (nop) (set (mem QI tmemaddr) tmpValReg)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

testsetht - testset HI indexed

machines: base

syntax: testseth $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x1	direction	0x0	rd6	rn6	rm6	0x1	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ((SI tmemaddr) (SI tmpValReg))
    (set tmpValReg rd6)
    (if f-addsubx
        (set tmemaddr (sub SI rn6 rm6))
        (set tmemaddr (add SI rn6 rm6)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_SHORT)
                   ((OPW_BYTE) (eq (and SI tmemaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI tmemaddr 1) 0))
                   ((OPW_WORD) (eq (and SI tmemaddr 3) 0))
                   (else (eq (and SI tmemaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr tmemaddr)
            (set rd6 (zext SI (mem HI tmemaddr))))))
    (if rd6 (nop) (set (mem HI tmemaddr) tmpValReg)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

testsett - testset SI indexed

machines: base

syntax: testset $rd6,[$rn6,$direction$rm6]

format:

31	30	29	28 27 26 25	24 23 22 21 20 19	18 17 16 15 14 13	12 11 10 9 8 7	6 5	4	3 2 1 0
f-dc-22-1	f-dc-21-1	f-addsubx	f-opc-19-4	f-rd6	f-rn6	f-rm6	f-wordsize	f-store	f-opc
0x0	0x1	direction	0x0	rd6	rn6	rm6	0x2	0x0	0x9

semantics:

(sequence
  ()
  (sequence
    ((SI tmemaddr) (SI tmpValReg))
    (set tmpValReg rd6)
    (if f-addsubx
        (set tmemaddr (sub SI rn6 rm6))
        (set tmemaddr (add SI rn6 rm6)))
    (sequence
      ((BI isAligmentAccess))
      (sequence
        ((BI scale))
        (set isAligmentAccess
             (case BI
                   (enum INT OPW_WORD)
                   ((OPW_BYTE) (eq (and SI tmemaddr 0) 0))
                   ((OPW_SHORT) (eq (and SI tmemaddr 1) 0))
                   ((OPW_WORD) (eq (and SI tmemaddr 3) 0))
                   (else (eq (and SI tmemaddr 7) 0))))
        (if (not BI isAligmentAccess)
            (if (eq gidisablebit 0)
                (if (eq (and USI (reg USI h-core-registers 9) 2) 0)
                    (sequence
                      ()
                      (set kmbit 1)
                      (set gidisablebit 1)
                      (set (reg USI h-core-registers 8) (add USI pc 2))
                      (set (reg USI h-core-registers 13)
                           (or USI (reg USI h-core-registers 13) 2))
                      (set pc 4))
                    (set (reg USI h-core-registers 10)
                         (or USI (reg USI h-core-registers 10) 2))))))
      (if (not BI (not BI isAligmentAccess))
          (sequence
            ()
            (set memaddr tmemaddr)
            (set rd6 (zext SI (mem SI tmemaddr))))))
    (if rd6 (nop) (set (mem SI tmemaddr) tmpValReg)))
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

trap16 - trap to simulator

machines: base

syntax: trap $trapnum6

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-trap-num f-trap-swi-9-1 f-opc-8-5 f-opc

trapnum6 0x1 0x1e 0x2

semantics:

(set (reg SI h-registers 0)
     (c-call SI "epiphany_trap" pc trapnum6))

unimpl - not-implemented

machines: base

syntax: unimpl

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opc-31-32

0xf000f

semantics:

(sequence
  ()
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

wand - wand

machines: base

syntax: wand

format:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-dc-15-7 f-opc-8-5 f-opc

0x0 0x18 0x2

semantics:

(sequence
  ()
  (set sflagbit 1)
  (sequence
    ((USI tmpPC))
    (if (eq pc (reg USI h-core-registers 7))
        (set (reg USI h-core-registers 5)
             (sub USI (reg USI h-core-registers 5) 1)))
    (if (and BI
             (eq pc (reg USI h-core-registers 7))
             (not BI (eq (reg USI h-core-registers 5) 0)))
        (set pc (reg USI h-core-registers 6)))))

Macro Instructions

Macro instructions for each machine:

epiphany32 - Adapteva EPIPHANY

epiphany32 - Adapteva EPIPHANY

beq16r - relaxable conditional branch
beq32r - relaxable conditional branch
bne16r - relaxable conditional branch
bne32r - relaxable conditional branch
bgtu16r - relaxable conditional branch
bgtu32r - relaxable conditional branch
bgteu16r - relaxable conditional branch
bgteu32r - relaxable conditional branch
blteu16r - relaxable conditional branch
blteu32r - relaxable conditional branch
bltu16r - relaxable conditional branch
bltu32r - relaxable conditional branch
bgt16r - relaxable conditional branch
bgt32r - relaxable conditional branch
bgte16r - relaxable conditional branch
bgte32r - relaxable conditional branch
blt16r - relaxable conditional branch
blt32r - relaxable conditional branch
blte16r - relaxable conditional branch
blte32r - relaxable conditional branch
bbeq16r - relaxable conditional branch
bbeq32r - relaxable conditional branch
bbne16r - relaxable conditional branch
bbne32r - relaxable conditional branch
bblt16r - relaxable conditional branch
bblt32r - relaxable conditional branch
bblte16r - relaxable conditional branch
bblte32r - relaxable conditional branch
b16r - relaxable b16
b32r - relaxable b
bl16r - bl16 relaxable
blr - bl relaxable
ldrbx - load QI indexed
ldrbp - load QI postmodify
ldrbd - load QI displacement
ldrbdpm - load QI displacement post-modify
ldrbds0 - load with 0 disp
ldrbdl0 - load with 0 disp
ldrbdl0.l - load with 0 disp
ldrhx - load HI indexed
ldrhp - load HI postmodify
ldrhd - load HI displacement
ldrhdpm - load HI displacement post-modify
ldrhds0 - load with 0 disp
ldrhdl0 - load with 0 disp
ldrhdl0.l - load with 0 disp
ldrx - load SI indexed
ldrp - load SI postmodify
ldrd - load SI displacement
ldrdpm - load SI displacement post-modify
ldrds0 - load with 0 disp
ldrdl0 - load with 0 disp
ldrdl0.l - load with 0 disp
ldrdx - load DI indexed
ldrdp - load DI postmodify
ldrdd - load DI displacement
ldrddpm - load DI displacement post-modify
ldrdds0 - load with 0 disp
ldrddl0 - load with 0 disp
ldrddl0.l - load with 0 disp
testsetbt.l - testset QI.l indexed
testsetht.l - testset HI.l indexed
testsett.l - testset SI.l indexed
strbx.l - storeQI indexed
strbp.l - store QI postmodify
strbd.l - store QI displacement
strbdpm.l - store QI displacement post-modify
strbds0 - store w 0 disp
strbdl0 - store w 0 disp
strbdl0.l - store w 0 disp
strhx.l - storeHI indexed
strhp.l - store HI postmodify
strhd.l - store HI displacement
strhdpm.l - store HI displacement post-modify
strhds0 - store w 0 disp
strhdl0 - store w 0 disp
strhdl0.l - store w 0 disp
strx.l - storeSI indexed
strp.l - store SI postmodify
strd.l - store SI displacement
strdpm.l - store SI displacement post-modify
strds0 - store w 0 disp
strdl0 - store w 0 disp
strdl0.l - store w 0 disp
strdx.l - storeDI indexed
strdp.l - store DI postmodify
strdd.l - store DI displacement
strddpm.l - store DI displacement post-modify
strdds0 - store w 0 disp
strddl0 - store w 0 disp
strddl0.l - store w 0 disp
cmov.lEQ - move register EQ
cmov.lNE - move register NE
cmov.lGTU - move register GTU
cmov.lGTEU - move register GTEU
cmov.lLTEU - move register LTEU
cmov.lLTU - move register LTU
cmov.lGT - move register GT
cmov.lGTE - move register GTE
cmov.lLT - move register LT
cmov.lLTE - move register LTE
cmov.lB - move register B
cmov.lBEQ - move register BEQ
cmov.lBNE - move register BNE
cmov.lBLT - move register BLT
cmov.lBLTE - move register BLTE
movts.l6 - move to 6
movts.ldma - move to dma
movts.lmem - move to mem
movts.lmesh - move to mesh
movfs.l6 - move from 6
movfs.ldma - move from dma
movfs.lmem - move from mem
movfs.lmesh - move from mesh
add.l - add
sub.l - sub
and.l - and
orr.l - orr
eor.l - eor
addir - relaxable short immediate add
addi32r - relaxed long immediate add
addi32m - relaxed long immediate add
subir - relaxable short immediate sub
subi32r - relaxed long immediate sub
subi32m - relaxed long immediate sub
asr.l - asr
lsr.l - lsr
lsl.l - lsl
lsri32.l - lsr
lsli32.l - lsl
asri32.l - asr
bitrl - bit reverse l
fext.l - fext
fdep.l - fdep
lfsr.l - lfsr
mov8r - mov imm8 relaxable
mov16r - mov imm16 relaxable
movtl - movt imm16
i_addf16 - i_add
f_addf32.l - f_add
i_addf32 - i_add
i_addf32.l - i_add
i_subf16 - i_sub
f_subf32.l - f_sub
i_subf32 - i_sub
i_subf32.l - i_sub
i_mulf16 - i_mul
f_mulf32.l - f_mul
i_mulf32 - i_mul
i_mulf32.l - i_mul
i_maddf16 - i_madd
f_maddf32.l - f_madd
i_maddf32 - i_madd
i_maddf32.l - i_madd
i_msubf16 - i_msub
f_msubf32.l - f_msub
i_msubf32 - i_msub
i_msubf32.l - i_msub
f_absf32.l - f_abs
f_loatf32.l - f_loat
f_ixf32.l - f_ix
f_recipf32.l - f_recip
f_sqrtf32.l - f_sqrt

Individual macro-instructions descriptions

add.l - add

syntax: add.l $rd6,$rn6,$rm6

transformation:
```
((emit add rd6 rn6 rm6))
```

addi32m - relaxed long immediate add

syntax: add $rd6,$rn6,$simm11

transformation:
```
((emit addi rd6 rn6 simm11))
```

addi32r - relaxed long immediate add

syntax: add $rd6,$rn6,$simm11

transformation:
```
((emit addi rd6 rn6 simm11))
```

addir - relaxable short immediate add

syntax: add $rd,$rn,$simm3

transformation:
```
((emit addi16 rd rn simm3))
```

and.l - and

syntax: and.l $rd6,$rn6,$rm6

transformation:
```
((emit and rd6 rn6 rm6))
```

asr.l - asr

syntax: asr.l $rd6,$rn6,$rm6

transformation:
```
((emit asr rd6 rn6 rm6))
```

asri32.l - asr

syntax: asr.l $rd6,$rn6,$shift

transformation:
```
((emit asri32 rd6 rn6 shift))
```

b16r - relaxable b16

syntax: b $simm8

transformation:
```
((emit b16 simm8))
```

b32r - relaxable b

syntax: b $simm24

transformation:
```
((emit b simm24))
```

bbeq16r - relaxable conditional branch

syntax: bbeq $simm8

transformation:
```
((emit bbeq16 simm8))
```

bbeq32r - relaxable conditional branch

syntax: bbeq $simm24

transformation:
```
((emit bbeq simm24))
```

bblt16r - relaxable conditional branch

syntax: bblt $simm8

transformation:
```
((emit bblt16 simm8))
```

bblt32r - relaxable conditional branch

syntax: bblt $simm24

transformation:
```
((emit bblt simm24))
```

bblte16r - relaxable conditional branch

syntax: bblte $simm8

transformation:
```
((emit bblte16 simm8))
```

bblte32r - relaxable conditional branch

syntax: bblte $simm24

transformation:
```
((emit bblte simm24))
```

bbne16r - relaxable conditional branch

syntax: bbne $simm8

transformation:
```
((emit bbne16 simm8))
```

bbne32r - relaxable conditional branch

syntax: bbne $simm24

transformation:
```
((emit bbne simm24))
```

beq16r - relaxable conditional branch

syntax: beq $simm8

transformation:
```
((emit beq16 simm8))
```

beq32r - relaxable conditional branch

syntax: beq $simm24

transformation:
```
((emit beq simm24))
```

bgt16r - relaxable conditional branch

syntax: bgt $simm8

transformation:
```
((emit bgt16 simm8))
```

bgt32r - relaxable conditional branch

syntax: bgt $simm24

transformation:
```
((emit bgt simm24))
```

bgte16r - relaxable conditional branch

syntax: bgte $simm8

transformation:
```
((emit bgte16 simm8))
```

bgte32r - relaxable conditional branch

syntax: bgte $simm24

transformation:
```
((emit bgte simm24))
```

bgteu16r - relaxable conditional branch

syntax: bgteu $simm8

transformation:
```
((emit bgteu16 simm8))
```

bgteu32r - relaxable conditional branch

syntax: bgteu $simm24

transformation:
```
((emit bgteu simm24))
```

bgtu16r - relaxable conditional branch

syntax: bgtu $simm8

transformation:
```
((emit bgtu16 simm8))
```

bgtu32r - relaxable conditional branch

syntax: bgtu $simm24

transformation:
```
((emit bgtu simm24))
```

bitrl - bit reverse l

syntax: bitr.l $rd6,$rn6

transformation:
```
((emit bitr rd6 rn6))
```

bl16r - bl16 relaxable

syntax: bl $simm8

transformation:
```
((emit bl16 simm8))
```

blr - bl relaxable

syntax: bl $simm24

transformation:
```
((emit bl simm24))
```

blt16r - relaxable conditional branch

syntax: blt $simm8

transformation:
```
((emit blt16 simm8))
```

blt32r - relaxable conditional branch

syntax: blt $simm24

transformation:
```
((emit blt simm24))
```

blte16r - relaxable conditional branch

syntax: blte $simm8

transformation:
```
((emit blte16 simm8))
```

blte32r - relaxable conditional branch

syntax: blte $simm24

transformation:
```
((emit blte simm24))
```

blteu16r - relaxable conditional branch

syntax: blteu $simm8

transformation:
```
((emit blteu16 simm8))
```

blteu32r - relaxable conditional branch

syntax: blteu $simm24

transformation:
```
((emit blteu simm24))
```

bltu16r - relaxable conditional branch

syntax: bltu $simm8

transformation:
```
((emit bltu16 simm8))
```

bltu32r - relaxable conditional branch

syntax: bltu $simm24

transformation:
```
((emit bltu simm24))
```

bne16r - relaxable conditional branch

syntax: bne $simm8

transformation:
```
((emit bne16 simm8))
```

bne32r - relaxable conditional branch

syntax: bne $simm24

transformation:
```
((emit bne simm24))
```

cmov.lB - move register B

syntax: mov.l $rd6,$rn6

transformation:
```
((emit cmovB rd6 rn6))
```

cmov.lBEQ - move register BEQ

syntax: movbeq.l $rd6,$rn6

transformation:
```
((emit cmovBEQ rd6 rn6))
```

cmov.lBLT - move register BLT

syntax: movblt.l $rd6,$rn6

transformation:
```
((emit cmovBLT rd6 rn6))
```

cmov.lBLTE - move register BLTE

syntax: movblte.l $rd6,$rn6

transformation:
```
((emit cmovBLTE rd6 rn6))
```

cmov.lBNE - move register BNE

syntax: movbne.l $rd6,$rn6

transformation:
```
((emit cmovBNE rd6 rn6))
```

cmov.lEQ - move register EQ

syntax: moveq.l $rd6,$rn6

transformation:
```
((emit cmovEQ rd6 rn6))
```

cmov.lGT - move register GT

syntax: movgt.l $rd6,$rn6

transformation:
```
((emit cmovGT rd6 rn6))
```

cmov.lGTE - move register GTE

syntax: movgte.l $rd6,$rn6

transformation:
```
((emit cmovGTE rd6 rn6))
```

cmov.lGTEU - move register GTEU

syntax: movgteu.l $rd6,$rn6

transformation:
```
((emit cmovGTEU rd6 rn6))
```

cmov.lGTU - move register GTU

syntax: movgtu.l $rd6,$rn6

transformation:
```
((emit cmovGTU rd6 rn6))
```

cmov.lLT - move register LT

syntax: movlt.l $rd6,$rn6

transformation:
```
((emit cmovLT rd6 rn6))
```

cmov.lLTE - move register LTE

syntax: movlte.l $rd6,$rn6

transformation:
```
((emit cmovLTE rd6 rn6))
```

cmov.lLTEU - move register LTEU

syntax: movlteu.l $rd6,$rn6

transformation:
```
((emit cmovLTEU rd6 rn6))
```

cmov.lLTU - move register LTU

syntax: movltu.l $rd6,$rn6

transformation:
```
((emit cmovLTU rd6 rn6))
```

cmov.lNE - move register NE

syntax: movne.l $rd6,$rn6

transformation:
```
((emit cmovNE rd6 rn6))
```

eor.l - eor

syntax: eor.l $rd6,$rn6,$rm6

transformation:
```
((emit eor rd6 rn6 rm6))
```

f_absf32.l - f_abs

syntax: fabs.l $rd6,$rn6

transformation:
```
((emit f_absf32 rd6 rn6))
```

f_addf32.l - f_add

syntax: fadd.l $rd6,$rn6,$rm6

transformation:
```
((emit f_addf32 rd6 rn6 rm6))
```

f_ixf32.l - f_ix

syntax: fix.l $rd6,$rn6

transformation:
```
((emit f_ixf32 rd6 rn6))
```

f_loatf32.l - f_loat

syntax: float.l $rd6,$rn6

transformation:
```
((emit f_loatf32 rd6 rn6))
```

f_maddf32.l - f_madd

syntax: fmadd.l $rd6,$rn6,$rm6

transformation:
```
((emit f_maddf32 rd6 rn6 rm6))
```

f_msubf32.l - f_msub

syntax: fmsub.l $rd6,$rn6,$rm6

transformation:
```
((emit f_msubf32 rd6 rn6 rm6))
```

f_mulf32.l - f_mul

syntax: fmul.l $rd6,$rn6,$rm6

transformation:
```
((emit f_mulf32 rd6 rn6 rm6))
```

f_recipf32.l - f_recip

syntax: frecip.l $frd6,$frn6

transformation:
```
((emit f_recipf32 frd6 frn6))
```

f_sqrtf32.l - f_sqrt

syntax: fsqrt.l $frd6,$frn6

transformation:
```
((emit f_sqrtf32 frd6 frn6))
```

f_subf32.l - f_sub

syntax: fsub.l $rd6,$rn6,$rm6

transformation:
```
((emit f_subf32 rd6 rn6 rm6))
```

fdep.l - fdep

syntax: fdep.l $rd6,$rn6,$rm6

transformation:
```
((emit fdep rd6 rn6 rm6))
```

fext.l - fext

syntax: fext.l $rd6,$rn6,$rm6

transformation:
```
((emit fext rd6 rn6 rm6))
```

i_addf16 - i_add

syntax: iadd $rd,$rn,$rm

transformation:
```
((emit f_addf16 rd rn rm))
```

i_addf32 - i_add

syntax: iadd $rd6,$rn6,$rm6

transformation:
```
((emit f_addf32 rd6 rn6 rm6))
```

i_addf32.l - i_add

syntax: iadd.l $rd6,$rn6,$rm6

transformation:
```
((emit f_addf32 rd6 rn6 rm6))
```

i_maddf16 - i_madd

syntax: imadd $rd,$rn,$rm

transformation:
```
((emit f_maddf16 rd rn rm))
```

i_maddf32 - i_madd

syntax: imadd $rd6,$rn6,$rm6

transformation:
```
((emit f_maddf32 rd6 rn6 rm6))
```

i_maddf32.l - i_madd

syntax: imadd.l $rd6,$rn6,$rm6

transformation:
```
((emit f_maddf32 rd6 rn6 rm6))
```

i_msubf16 - i_msub

syntax: imsub $rd,$rn,$rm

transformation:
```
((emit f_msubf16 rd rn rm))
```

i_msubf32 - i_msub

syntax: imsub $rd6,$rn6,$rm6

transformation:
```
((emit f_msubf32 rd6 rn6 rm6))
```

i_msubf32.l - i_msub

syntax: imsub.l $rd6,$rn6,$rm6

transformation:
```
((emit f_msubf32 rd6 rn6 rm6))
```

i_mulf16 - i_mul

syntax: imul $rd,$rn,$rm

transformation:
```
((emit f_mulf16 rd rn rm))
```

i_mulf32 - i_mul

syntax: imul $rd6,$rn6,$rm6

transformation:
```
((emit f_mulf32 rd6 rn6 rm6))
```

i_mulf32.l - i_mul

syntax: imul.l $rd6,$rn6,$rm6

transformation:
```
((emit f_mulf32 rd6 rn6 rm6))
```

i_subf16 - i_sub

syntax: isub $rd,$rn,$rm

transformation:
```
((emit f_subf16 rd rn rm))
```

i_subf32 - i_sub

syntax: isub $rd6,$rn6,$rm6

transformation:
```
((emit f_subf32 rd6 rn6 rm6))
```

i_subf32.l - i_sub

syntax: isub.l $rd6,$rn6,$rm6

transformation:
```
((emit f_subf32 rd6 rn6 rm6))
```

ldrbd - load QI displacement

syntax: ldrb.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit ldrbd.l rd6 rn6 dpmi disp11))
```

ldrbdl0 - load with 0 disp

syntax: ldrb $rd6,[$rn6]

transformation:

((emit ldrbd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrbdl0.l - load with 0 disp

syntax: ldrb.l $rd6,[$rn6]

transformation:

((emit ldrbd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrbdpm - load QI displacement post-modify

syntax: ldrb.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit ldrbdpm.l rd6 rn6 dpmi disp11))
```

ldrbds0 - load with 0 disp

syntax: ldrb $rd,[$rn]

transformation:
```
((emit ldrbd16.s rd rn (disp3 0)))
```

ldrbp - load QI postmodify

syntax: ldrb.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit ldrbp.l rd6 rn6 direction rm6))
```

ldrbx - load QI indexed

syntax: ldrb.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit ldrbx.l rd6 rn6 direction rm6))
```

ldrd - load SI displacement

syntax: ldr.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit ldrd.l rd6 rn6 dpmi disp11))
```

ldrdd - load DI displacement

syntax: ldrd.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit ldrdd.l rd6 rn6 dpmi disp11))
```

ldrddl0 - load with 0 disp

syntax: ldrd $rd6,[$rn6]

transformation:

((emit ldrdd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrddl0.l - load with 0 disp

syntax: ldrd.l $rd6,[$rn6]

transformation:

((emit ldrdd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrddpm - load DI displacement post-modify

syntax: ldrd.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit ldrddpm.l rd6 rn6 dpmi disp11))
```

ldrdds0 - load with 0 disp

syntax: ldrd $rd,[$rn]

transformation:
```
((emit ldrdd16.s rd rn (disp3 0)))
```

ldrdl0 - load with 0 disp

syntax: ldr $rd6,[$rn6]

transformation:

((emit ldrd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrdl0.l - load with 0 disp

syntax: ldr.l $rd6,[$rn6]

transformation:

((emit ldrd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrdp - load DI postmodify

syntax: ldrd.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit ldrdp.l rd6 rn6 direction rm6))
```

ldrdpm - load SI displacement post-modify

syntax: ldr.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit ldrdpm.l rd6 rn6 dpmi disp11))
```

ldrds0 - load with 0 disp

syntax: ldr $rd,[$rn]

transformation:
```
((emit ldrd16.s rd rn (disp3 0)))
```

ldrdx - load DI indexed

syntax: ldrd.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit ldrdx.l rd6 rn6 direction rm6))
```

ldrhd - load HI displacement

syntax: ldrh.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit ldrhd.l rd6 rn6 dpmi disp11))
```

ldrhdl0 - load with 0 disp

syntax: ldrh $rd6,[$rn6]

transformation:

((emit ldrhd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrhdl0.l - load with 0 disp

syntax: ldrh.l $rd6,[$rn6]

transformation:

((emit ldrhd.l rd6 rn6 (dpmi 0) (disp11 0)))

ldrhdpm - load HI displacement post-modify

syntax: ldrh.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit ldrhdpm.l rd6 rn6 dpmi disp11))
```

ldrhds0 - load with 0 disp

syntax: ldrh $rd,[$rn]

transformation:
```
((emit ldrhd16.s rd rn (disp3 0)))
```

ldrhp - load HI postmodify

syntax: ldrh.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit ldrhp.l rd6 rn6 direction rm6))
```

ldrhx - load HI indexed

syntax: ldrh.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit ldrhx.l rd6 rn6 direction rm6))
```

ldrp - load SI postmodify

syntax: ldr.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit ldrp.l rd6 rn6 direction rm6))
```

ldrx - load SI indexed

syntax: ldr.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit ldrx.l rd6 rn6 direction rm6))
```

lfsr.l - lfsr

syntax: lfsr.l $rd6,$rn6,$rm6

transformation:
```
((emit lfsr rd6 rn6 rm6))
```

lsl.l - lsl

syntax: lsl.l $rd6,$rn6,$rm6

transformation:
```
((emit lsl rd6 rn6 rm6))
```

lsli32.l - lsl

syntax: lsl.l $rd6,$rn6,$shift

transformation:
```
((emit lsli32 rd6 rn6 shift))
```

lsr.l - lsr

syntax: lsr.l $rd6,$rn6,$rm6

transformation:
```
((emit lsr rd6 rn6 rm6))
```

lsri32.l - lsr

syntax: lsr.l $rd6,$rn6,$shift

transformation:
```
((emit lsri32 rd6 rn6 shift))
```

mov16r - mov imm16 relaxable

syntax: mov $rd6,$imm16

transformation:
```
((emit mov16 rd6 imm16))
```

mov8r - mov imm8 relaxable

syntax: mov $rd,$imm8

transformation:
```
((emit mov8 rd imm8))
```

movfs.l6 - move from 6

syntax: movfs.l $rd6,$sn6

transformation:
```
((emit movfs6 rd6 sn6))
```

movfs.ldma - move from dma

syntax: movfs.l $rd6,$sndma

transformation:
```
((emit movfsdma rd6 sndma))
```

movfs.lmem - move from mem

syntax: movfs.l $rd6,$snmem

transformation:
```
((emit movfsmem rd6 snmem))
```

movfs.lmesh - move from mesh

syntax: movfs.l $rd6,$snmesh

transformation:
```
((emit movfsmesh rd6 snmesh))
```

movtl - movt imm16

syntax: movt.l $rd6,$imm16

transformation:
```
((emit movt rd6 imm16))
```

movts.l6 - move to 6

syntax: movts.l $sn6,$rd6

transformation:
```
((emit movts6 sn6 rd6))
```

movts.ldma - move to dma

syntax: movts.l $sndma,$rd6

transformation:
```
((emit movtsdma sndma rd6))
```

movts.lmem - move to mem

syntax: movts.l $snmem,$rd6

transformation:
```
((emit movtsmem snmem rd6))
```

movts.lmesh - move to mesh

syntax: movts.l $snmesh,$rd6

transformation:
```
((emit movtsmesh snmesh rd6))
```

orr.l - orr

syntax: orr.l $rd6,$rn6,$rm6

transformation:
```
((emit orr rd6 rn6 rm6))
```

strbd.l - store QI displacement

syntax: strb.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit strbd rd6 rn6 dpmi disp11))
```

strbdl0 - store w 0 disp

syntax: strb $rd6,[$rn6]

transformation:

((emit strbd rd6 rn6 (dpmi 0) (disp11 0)))

strbdl0.l - store w 0 disp

syntax: strb.l $rd6,[$rn6]

transformation:

((emit strbd rd6 rn6 (dpmi 0) (disp11 0)))

strbdpm.l - store QI displacement post-modify

syntax: strb.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit strbdpm rd6 rn6 dpmi disp11))
```

strbds0 - store w 0 disp

syntax: strb $rd,[$rn]

transformation:
```
((emit strbd16 rd rn (disp3 0)))
```

strbp.l - store QI postmodify

syntax: strb.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit strbp rd6 rn6 direction rm6))
```

strbx.l - storeQI indexed

syntax: strb.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit strbx rd6 rn6 direction rm6))
```

strd.l - store SI displacement

syntax: str.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit strd rd6 rn6 dpmi disp11))
```

strdd.l - store DI displacement

syntax: strd.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit strdd rd6 rn6 dpmi disp11))
```

strddl0 - store w 0 disp

syntax: strd $rd6,[$rn6]

transformation:

((emit strdd rd6 rn6 (dpmi 0) (disp11 0)))

strddl0.l - store w 0 disp

syntax: strd.l $rd6,[$rn6]

transformation:

((emit strdd rd6 rn6 (dpmi 0) (disp11 0)))

strddpm.l - store DI displacement post-modify

syntax: strd.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit strddpm rd6 rn6 dpmi disp11))
```

strdds0 - store w 0 disp

syntax: strd $rd,[$rn]

transformation:
```
((emit strdd16 rd rn (disp3 0)))
```

strdl0 - store w 0 disp

syntax: str $rd6,[$rn6]

transformation:

((emit strd rd6 rn6 (dpmi 0) (disp11 0)))

strdl0.l - store w 0 disp

syntax: str.l $rd6,[$rn6]

transformation:

((emit strd rd6 rn6 (dpmi 0) (disp11 0)))

strdp.l - store DI postmodify

syntax: strd.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit strdp rd6 rn6 direction rm6))
```

strdpm.l - store SI displacement post-modify

syntax: str.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit strdpm rd6 rn6 dpmi disp11))
```

strds0 - store w 0 disp

syntax: str $rd,[$rn]

transformation:
```
((emit strd16 rd rn (disp3 0)))
```

strdx.l - storeDI indexed

syntax: strd.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit strdx rd6 rn6 direction rm6))
```

strhd.l - store HI displacement

syntax: strh.l $rd6,[$rn6,$dpmi$disp11]

transformation:
```
((emit strhd rd6 rn6 dpmi disp11))
```

strhdl0 - store w 0 disp

syntax: strh $rd6,[$rn6]

transformation:

((emit strhd rd6 rn6 (dpmi 0) (disp11 0)))

strhdl0.l - store w 0 disp

syntax: strh.l $rd6,[$rn6]

transformation:

((emit strhd rd6 rn6 (dpmi 0) (disp11 0)))

strhdpm.l - store HI displacement post-modify

syntax: strh.l $rd6,[$rn6],$dpmi$disp11

transformation:
```
((emit strhdpm rd6 rn6 dpmi disp11))
```

strhds0 - store w 0 disp

syntax: strh $rd,[$rn]

transformation:
```
((emit strhd16 rd rn (disp3 0)))
```

strhp.l - store HI postmodify

syntax: strh.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit strhp rd6 rn6 direction rm6))
```

strhx.l - storeHI indexed

syntax: strh.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit strhx rd6 rn6 direction rm6))
```

strp.l - store SI postmodify

syntax: str.l $rd6,[$rn6],$direction$rm6

transformation:
```
((emit strp rd6 rn6 direction rm6))
```

strx.l - storeSI indexed

syntax: str.l $rd6,[$rn6,$direction$rm6]

transformation:
```
((emit strx rd6 rn6 direction rm6))
```

sub.l - sub

syntax: sub.l $rd6,$rn6,$rm6

transformation:
```
((emit sub rd6 rn6 rm6))
```

subi32m - relaxed long immediate sub

syntax: sub $rd6,$rn6,$simm11

transformation:
```
((emit subi rd6 rn6 simm11))
```

subi32r - relaxed long immediate sub

syntax: sub $rd6,$rn6,$simm11

transformation:
```
((emit subi rd6 rn6 simm11))
```

subir - relaxable short immediate sub

syntax: sub $rd,$rn,$simm3

transformation:
```
((emit subi16 rd rn simm3))
```

testsetbt.l - testset QI.l indexed

syntax: testsetb.l $rd6,[$rn6,$direction$rm6]

transformation:

((emit testsetbt rd6 rn6 direction rm6))

testsetht.l - testset HI.l indexed

syntax: testseth.l $rd6,[$rn6,$direction$rm6]

transformation:

((emit testsetht rd6 rn6 direction rm6))

testsett.l - testset SI.l indexed

syntax: testset.l $rd6,[$rn6,$direction$rm6]

transformation:

((emit testsett rd6 rn6 direction rm6))

This documentation was machine generated from the cgen cpu description files for this architecture.
https://sourceware.org/cgen/

15 14 13	12 11 10	9 8 7	6 5 4	3 2 1 0
f-rd	f-rn	f-rm	f-opc-6-3	f-opc
rd	rn	rm	0x1	0xa

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8	7 6 5 4	3 2 1 0
f-simm24	f-condcode	f-opc
simm24	0xe	0x8

15 14 13 12 11 10 9 8	7 6 5 4	3 2 1 0
f-simm8	f-condcode	f-opc
simm8	0xe	0x0

15 14 13 12 11 10 9	8 7 6 5 4	3 2 1 0
f-dc-15-7	f-opc-8-5	f-opc
0x0	0x1c	0x2

15 14 13	12 11 10 9 8 7 6 5	4	3 2 1 0
f-rd	f-imm8	f-opc-4-1	f-opc
rd	imm8	0x0	0x3

Instructions

epiphany32 ALU - ALU

epiphany32 BR - Branch

epiphany32 epiphany32 - Adapteva EPIPHANY

Individual instructions descriptions

add - add

add16 - add

addi - add

addi16 - add

and - and

and16 - and

asr - asr

asr16 - asr

asri16 - asr

asri32 - asr

b - long unconditional branch

b16 - short unconditional branch

bbeq - Conditional Branch beq

bbeq16 - Conditional Branch - 16 bitbeq

bblt - Conditional Branch blt

bblt16 - Conditional Branch - 16 bitblt

bblte - Conditional Branch blte

bblte16 - Conditional Branch - 16 bitblte

bbne - Conditional Branch bne

bbne16 - Conditional Branch - 16 bitbne

beq - Conditional Branch eq

beq16 - Conditional Branch - 16 biteq

bgt - Conditional Branch gt

bgt16 - Conditional Branch - 16 bitgt

bgte - Conditional Branch gte

bgte16 - Conditional Branch - 16 bitgte

bgteu - Conditional Branch gteu

bgteu16 - Conditional Branch - 16 bitgteu

bgtu - Conditional Branch gtu

bgtu16 - Conditional Branch - 16 bitgtu

bitr - bit reverse

bitr16 - bit reverse short

bkpt - breakpoint

bl - branch and link

bl16 - branch and link

blt - Conditional Branch lt

blt16 - Conditional Branch - 16 bitlt

blte - Conditional Branch lte

blte16 - Conditional Branch - 16 bitlte

blteu - Conditional Branch lteu

blteu16 - Conditional Branch - 16 bitlteu

bltu - Conditional Branch ltu

bltu16 - Conditional Branch - 16 bitltu

bne - Conditional Branch ne

bne16 - Conditional Branch - 16 bitne

cmov16B - move register B

cmov16BEQ - move register BEQ

cmov16BLT - move register BLT

cmov16BLTE - move register BLTE

cmov16BNE - move register BNE

cmov16EQ - move register EQ

cmov16GT - move register GT

cmov16GTE - move register GTE

cmov16GTEU - move register GTEU

cmov16GTU - move register GTU

cmov16LT - move register LT

cmov16LTE - move register LTE

cmov16LTEU - move register LTEU

cmov16LTU - move register LTU

cmov16NE - move register NE

cmovB - move register B

cmovBEQ - move register BEQ

cmovBLT - move register BLT

cmovBLTE - move register BLTE

cmovBNE - move register BNE

cmovEQ - move register EQ

cmovGT - move register GT

cmovGTE - move register GTE

cmovGTEU - move register GTEU

cmovGTU - move register GTU

cmovLT - move register LT

cmovLTE - move register LTE

cmovLTEU - move register LTEU

cmovLTU - move register LTU

cmovNE - move register NE