FR30 Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
FR30 Architecture
This section describes various things about the cgen description of
the FR30 architecture.  Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): msb = 0
ISA description
- 
fr30 - 
 
- default-insn-word-bitsize: 16
 
- default-insn-bitsize: 16
 
- base-insn-bitsize: 16
 
- decode-assist:  0 1 2 3 4 5 6 7
 
- decode-splits: 
 
 
CPU Families
- 
fr30bf - Fujitsu FR30 base family
 
 Machines:
- 
fr30 - Generic FR30 cpu
 
 Models:
 
 
Machine variants
fr30 - Generic FR30 cpu
- 
bfd-name: fr30
- 
isas:  fr30
Model variants
fr30-1 - fr30-1
Registers
h-cbit - carry            bit
- 
machines:  base
- 
bitsize: 1
h-ccr - condition code bits
- 
machines:  base
- 
bitsize: 8
h-cr - coprocessor registers
- 
machines:  base
- 
bitsize: 32
- 
array: [16]
 names:
 
 
| cr0 | 0 |  
| cr1 | 1 |  
| cr2 | 2 |  
| cr3 | 3 |  
| cr4 | 4 |  
| cr5 | 5 |  
| cr6 | 6 |  
| cr7 | 7 |  
| cr8 | 8 |  
| cr9 | 9 |  
| cr10 | 10 |  
| cr11 | 11 |  
| cr12 | 12 |  
| cr13 | 13 |  
| cr14 | 14 |  
| cr15 | 15 |  h-d0bit - division 0       bit
- 
machines:  base
- 
bitsize: 1
 h-d1bit - division 1       bit
- 
machines:  base
- 
bitsize: 1
 h-dr - dedicated registers
- 
machines:  base
- 
bitsize: 32
- 
array: [6]
 names:
 
 
| tbr | 0 |  
| rp | 1 |  
| ssp | 2 |  
| usp | 3 |  
| mdh | 4 |  
| mdl | 5 |  h-gr - general registers
- 
machines:  base
- 
bitsize: 32
- 
array: [16]
 names:
 
 
| r0 | 0 |  
| r1 | 1 |  
| r2 | 2 |  
| r3 | 3 |  
| r4 | 4 |  
| r5 | 5 |  
| r6 | 6 |  
| r7 | 7 |  
| r8 | 8 |  
| r9 | 9 |  
| r10 | 10 |  
| r11 | 11 |  
| r12 | 12 |  
| r13 | 13 |  
| r14 | 14 |  
| r15 | 15 |  
| ac | 13 |  
| fp | 14 |  
| sp | 15 |  h-ibit - interrupt enable bit
- 
machines:  base
- 
bitsize: 1
 h-ilm - interrupt level mask
- 
machines:  base
- 
bitsize: 8
 h-nbit - negative         bit
- 
machines:  base
- 
bitsize: 1
 h-pc - program counter
- 
machines:  base
- 
bitsize: 32
 h-ps - processor status
- 
machines:  base
- 
bitsize: 32
 h-r13 - General Register 13 explicitly required
- 
machines:  base
- 
bitsize: 32
 h-r14 - General Register 14 explicitly required
- 
machines:  base
- 
bitsize: 32
 h-r15 - General Register 15 explicitly required
- 
machines:  base
- 
bitsize: 32
 h-sbit - stack bit
- 
machines:  base
- 
bitsize: 1
 h-scr - system condition bits
- 
machines:  base
- 
bitsize: 8
 h-tbit - trace trap       bit
- 
machines:  base
- 
bitsize: 1
 h-vbit - overflow         bit
- 
machines:  base
- 
bitsize: 1
 h-zbit - zero             bit
- 
machines:  base
- 
bitsize: 1
 
 Assembler supplemental
 
This documentation was machine generated from the cgen cpu description
files for this architecture.
 https://sourceware.org/cgen/