0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | src1 |
(set dst (add SI src1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | lit1 |
(set dst (add UINT lit1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | src1 |
(set dst (add SI src1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | lit1 |
(set dst (add UINT lit1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | src1 |
(set dst (and SI src1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | lit1 |
(set dst (and UINT lit1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | src1 |
(set dst (and SI src1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | lit1 |
(set dst (and UINT lit1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x2 | 0x0 | src1 |
(set dst (and SI src2 (inv SI src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x2 | 0x0 | lit1 |
(set dst (and SI src2 (inv UINT lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x2 | 0x0 | src1 |
(set dst (and UINT lit2 (inv SI src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x2 | 0x0 | lit1 |
(set dst (and UINT lit2 (inv UINT lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x8 | ctrl_disp | 0x0 |
(set pc ctrl_disp)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x30 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (eq (and WI (sll WI 1 br_lit1) br_src2) 0) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x30 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (eq (and WI (sll WI 1 br_src1) br_src2) 0) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x37 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (ne (and WI (sll WI 1 br_lit1) br_src2) 0) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x37 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (ne (and WI (sll WI 1 br_src1) br_src2) 0) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x12 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 2) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x11 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 1) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x13 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 3) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x14 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 4) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x16 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 6) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x15 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 5) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x10 | ctrl_disp | 0x0 |
(if (eq (reg SI h-cc 0) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0x17 | ctrl_disp | 0x0 |
(if (ne (and SI (reg SI h-cc 0) 7) 0) (set pc ctrl_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x84 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set pc optdisp)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x84 | dst | abase | 0x4 | scale | 0x0 | indx |
(set pc abase)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x84 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set pc (add UINT optdisp abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x84 | dst | abase | 0x7 | scale | 0x0 | indx |
(set pc (add SI abase (mul SI indx (sll SI 1 scale))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x84 | dst | abase | 0x1 | 0x0 | offset |
(set pc (add UINT offset abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x66 | dst | src2 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | src1 |
(set pc (c-call WI "i960_trap" pc src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x86 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(sequence ((WI temp)) (set temp (and SI (add SI (reg SI h-gr 1) 63) (inv SI 63))) (set (reg SI h-gr 2) (add USI pc 8)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 0)) (reg SI h-gr 0)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 4)) (reg SI h-gr 1)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 8)) (reg SI h-gr 2)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 12)) (reg SI h-gr 3)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 16)) (reg SI h-gr 4)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 20)) (reg SI h-gr 5)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 24)) (reg SI h-gr 6)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 28)) (reg SI h-gr 7)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 32)) (reg SI h-gr 8)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 36)) (reg SI h-gr 9)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 40)) (reg SI h-gr 10)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 44)) (reg SI h-gr 11)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 48)) (reg SI h-gr 12)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 52)) (reg SI h-gr 13)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 56)) (reg SI h-gr 14)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 60)) (reg SI h-gr 15)) (set pc optdisp) (set-quiet (reg SI h-gr 0) 3735928559) (set-quiet (reg SI h-gr 1) 3735928559) (set-quiet (reg SI h-gr 2) 3735928559) (set-quiet (reg SI h-gr 3) 3735928559) (set-quiet (reg SI h-gr 4) 3735928559) (set-quiet (reg SI h-gr 5) 3735928559) (set-quiet (reg SI h-gr 6) 3735928559) (set-quiet (reg SI h-gr 7) 3735928559) (set-quiet (reg SI h-gr 8) 3735928559) (set-quiet (reg SI h-gr 9) 3735928559) (set-quiet (reg SI h-gr 10) 3735928559) (set-quiet (reg SI h-gr 11) 3735928559) (set-quiet (reg SI h-gr 12) 3735928559) (set-quiet (reg SI h-gr 13) 3735928559) (set-quiet (reg SI h-gr 14) 3735928559) (set-quiet (reg SI h-gr 15) 3735928559) (set (reg SI h-gr 0) (reg SI h-gr 31)) (set (reg SI h-gr 31) temp) (set (reg SI h-gr 1) (add SI temp 64)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x86 | dst | abase | 0x4 | scale | 0x0 | indx |
(sequence ((WI temp)) (set temp (and SI (add SI (reg SI h-gr 1) 63) (inv SI 63))) (set (reg SI h-gr 2) (add USI pc 4)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 0)) (reg SI h-gr 0)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 4)) (reg SI h-gr 1)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 8)) (reg SI h-gr 2)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 12)) (reg SI h-gr 3)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 16)) (reg SI h-gr 4)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 20)) (reg SI h-gr 5)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 24)) (reg SI h-gr 6)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 28)) (reg SI h-gr 7)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 32)) (reg SI h-gr 8)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 36)) (reg SI h-gr 9)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 40)) (reg SI h-gr 10)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 44)) (reg SI h-gr 11)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 48)) (reg SI h-gr 12)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 52)) (reg SI h-gr 13)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 56)) (reg SI h-gr 14)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 60)) (reg SI h-gr 15)) (set pc abase) (set-quiet (reg SI h-gr 0) 3735928559) (set-quiet (reg SI h-gr 1) 3735928559) (set-quiet (reg SI h-gr 2) 3735928559) (set-quiet (reg SI h-gr 3) 3735928559) (set-quiet (reg SI h-gr 4) 3735928559) (set-quiet (reg SI h-gr 5) 3735928559) (set-quiet (reg SI h-gr 6) 3735928559) (set-quiet (reg SI h-gr 7) 3735928559) (set-quiet (reg SI h-gr 8) 3735928559) (set-quiet (reg SI h-gr 9) 3735928559) (set-quiet (reg SI h-gr 10) 3735928559) (set-quiet (reg SI h-gr 11) 3735928559) (set-quiet (reg SI h-gr 12) 3735928559) (set-quiet (reg SI h-gr 13) 3735928559) (set-quiet (reg SI h-gr 14) 3735928559) (set-quiet (reg SI h-gr 15) 3735928559) (set (reg SI h-gr 0) (reg SI h-gr 31)) (set (reg SI h-gr 31) temp) (set (reg SI h-gr 1) (add SI temp 64)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x86 | dst | abase | 0x1 | 0x0 | offset |
(sequence ((WI temp)) (set temp (and SI (add SI (reg SI h-gr 1) 63) (inv SI 63))) (set (reg SI h-gr 2) (add USI pc 4)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 0)) (reg SI h-gr 0)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 4)) (reg SI h-gr 1)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 8)) (reg SI h-gr 2)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 12)) (reg SI h-gr 3)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 16)) (reg SI h-gr 4)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 20)) (reg SI h-gr 5)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 24)) (reg SI h-gr 6)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 28)) (reg SI h-gr 7)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 32)) (reg SI h-gr 8)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 36)) (reg SI h-gr 9)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 40)) (reg SI h-gr 10)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 44)) (reg SI h-gr 11)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 48)) (reg SI h-gr 12)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 52)) (reg SI h-gr 13)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 56)) (reg SI h-gr 14)) (set-quiet (mem WI (add SI (reg SI h-gr 31) 60)) (reg SI h-gr 15)) (set pc (add UINT offset abase)) (set-quiet (reg SI h-gr 0) 3735928559) (set-quiet (reg SI h-gr 1) 3735928559) (set-quiet (reg SI h-gr 2) 3735928559) (set-quiet (reg SI h-gr 3) 3735928559) (set-quiet (reg SI h-gr 4) 3735928559) (set-quiet (reg SI h-gr 5) 3735928559) (set-quiet (reg SI h-gr 6) 3735928559) (set-quiet (reg SI h-gr 7) 3735928559) (set-quiet (reg SI h-gr 8) 3735928559) (set-quiet (reg SI h-gr 9) 3735928559) (set-quiet (reg SI h-gr 10) 3735928559) (set-quiet (reg SI h-gr 11) 3735928559) (set-quiet (reg SI h-gr 12) 3735928559) (set-quiet (reg SI h-gr 13) 3735928559) (set-quiet (reg SI h-gr 14) 3735928559) (set-quiet (reg SI h-gr 15) 3735928559) (set (reg SI h-gr 0) (reg SI h-gr 31)) (set (reg SI h-gr 31) temp) (set (reg SI h-gr 1) (add SI temp 64)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xc | 0x0 | src1 |
(set dst (and SI (inv SI (sll SI 1 src1)) src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xc | 0x0 | lit1 |
(set dst (and SI (inv SI (sll SI 1 lit1)) src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xc | 0x0 | src1 |
(set dst (and SI (inv SI (sll SI 1 src1)) lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xc | 0x0 | lit1 |
(set dst (and SI (inv SI (sll SI 1 lit1)) lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | src2 | 0x1 | 0x0 | 0x0 | 0x1 | 0x0 | src1 |
(set (reg SI h-cc 0) (cond WI ((lt src1 src2) 4) ((eq src1 src2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | src2 | 0x1 | 0x0 | 0x1 | 0x1 | 0x0 | lit1 |
(set (reg SI h-cc 0) (cond WI ((lt lit1 src2) 4) ((eq lit1 src2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | lit2 | 0x1 | 0x1 | 0x0 | 0x1 | 0x0 | src1 |
(set (reg SI h-cc 0) (cond WI ((lt src1 lit2) 4) ((eq src1 lit2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | lit2 | 0x1 | 0x1 | 0x1 | 0x1 | 0x0 | lit1 |
(set (reg SI h-cc 0) (cond WI ((lt lit1 lit2) 4) ((eq lit1 lit2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3a | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (eq br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3a | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (eq br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x39 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (gt br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x39 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (gt br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3b | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (ge br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3b | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (ge br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3c | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (lt br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3c | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (lt br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3e | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (le br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3e | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (le br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3d | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (ne br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x3d | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (ne br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | src2 | 0x1 | 0x0 | 0x0 | 0x0 | 0x0 | src1 |
(set (reg SI h-cc 0) (cond WI ((ltu src1 src2) 4) ((eq src1 src2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | src2 | 0x1 | 0x0 | 0x1 | 0x0 | 0x0 | lit1 |
(set (reg SI h-cc 0) (cond WI ((ltu lit1 src2) 4) ((eq lit1 src2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | lit2 | 0x1 | 0x1 | 0x0 | 0x0 | 0x0 | src1 |
(set (reg SI h-cc 0) (cond WI ((ltu src1 lit2) 4) ((eq src1 lit2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5a | dst | lit2 | 0x1 | 0x1 | 0x1 | 0x0 | 0x0 | lit1 |
(set (reg SI h-cc 0) (cond WI ((ltu lit1 lit2) 4) ((eq lit1 lit2) 2) (else . 1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x32 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (eq br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x32 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (eq br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x31 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (gtu br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x31 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (gtu br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x33 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (geu br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x33 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (geu br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x34 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (ltu br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x34 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (ltu br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x36 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (leu br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x36 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (leu br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x35 | br_lit1 | br_src2 | 0x1 | br_disp | 0x0 |
(if (ne br_lit1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x35 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(if (ne br_src1 br_src2) (set pc br_disp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xb | 0x0 | src1 |
(set dst (div SI src2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (div SI src2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xb | 0x0 | src1 |
(set dst (div UINT lit2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (div UINT lit2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xb | 0x0 | src1 |
(set dst (udiv SI src2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (udiv SI src2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xb | 0x0 | src1 |
(set dst (udiv UINT lit2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (udiv UINT lit2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x67 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | src1 |
(sequence ((DI temp) (SI dregno)) (set temp (mul DI (zext DI src1) (zext DI src2))) (set dregno f-srcdst) (set dst (trunc SI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (trunc SI (srl DI temp 32))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x67 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | lit1 |
(sequence ((DI temp) (SI dregno)) (set temp (mul DI (zext DI lit1) (zext DI src2))) (set dregno f-srcdst) (set dst (trunc SI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (trunc SI (srl DI temp 32))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x67 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | src1 |
(sequence ((DI temp) (SI dregno)) (set temp (mul DI (zext DI src1) (zext DI lit2))) (set dregno f-srcdst) (set dst (trunc SI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (trunc SI (srl DI temp 32))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x67 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | lit1 |
(sequence ((DI temp) (SI dregno)) (set temp (mul DI (zext DI lit1) (zext DI lit2))) (set dregno f-srcdst) (set dst (trunc SI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (trunc SI (srl DI temp 32))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x66 | dst | src2 | 0x1 | 0x1 | 0x1 | 0xd | 0x0 | src1 |
(nop)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x66 | dst | src2 | 0x1 | 0x1 | 0x1 | 0xc | 0x0 | src1 |
(set pc (c-call WI "i960_breakpoint" pc))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x90 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set dst (mem WI optdisp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x90 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(set dst (mem WI (add UINT optdisp (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x90 | dst | abase | 0x4 | scale | 0x0 | indx |
(set dst (mem WI abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x90 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set dst (mem WI (add UINT optdisp abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x90 | dst | abase | 0x7 | scale | 0x0 | indx |
(set dst (mem WI (add SI abase (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x90 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(set dst (mem WI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x90 | dst | abase | 0x1 | 0x0 | offset |
(set dst (mem WI (add UINT offset abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x90 | dst | abase | 0x0 | 0x0 | offset |
(set dst (mem WI offset))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8c | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set dst optdisp)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8c | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(set dst (add UINT optdisp (mul SI indx (sll SI 1 scale))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8c | dst | abase | 0x4 | scale | 0x0 | indx |
(set dst abase)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8c | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set dst (add UINT optdisp abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8c | dst | abase | 0x7 | scale | 0x0 | indx |
(set dst (add SI abase (mul SI indx (sll SI 1 scale))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8c | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(set dst (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x8c | dst | abase | 0x1 | 0x0 | offset |
(set dst (add UINT offset abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x8c | dst | abase | 0x0 | 0x0 | offset |
(set dst offset)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc0 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set dst (mem QI optdisp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc0 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(set dst (mem QI (add UINT optdisp (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc0 | dst | abase | 0x4 | scale | 0x0 | indx |
(set dst (mem QI abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc0 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set dst (mem QI (add UINT optdisp abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc0 | dst | abase | 0x7 | scale | 0x0 | indx |
(set dst (mem QI (add SI abase (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc0 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(set dst (mem QI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xc0 | dst | abase | 0x1 | 0x0 | offset |
(set dst (mem QI (add UINT offset abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xc0 | dst | abase | 0x0 | 0x0 | offset |
(set dst (mem QI offset))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc8 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set dst (mem HI optdisp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc8 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(set dst (mem HI (add UINT optdisp (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc8 | dst | abase | 0x4 | scale | 0x0 | indx |
(set dst (mem HI abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc8 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set dst (mem HI (add UINT optdisp abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc8 | dst | abase | 0x7 | scale | 0x0 | indx |
(set dst (mem HI (add SI abase (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xc8 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(set dst (mem HI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xc8 | dst | abase | 0x1 | 0x0 | offset |
(set dst (mem HI (add UINT offset abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xc8 | dst | abase | 0x0 | 0x0 | offset |
(set dst (mem HI offset))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x98 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp optdisp) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x98 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp (mul SI indx (sll SI 1 scale)))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x98 | dst | abase | 0x4 | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp abase) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x98 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp abase)) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x98 | dst | abase | 0x7 | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add SI abase (mul SI indx (sll SI 1 scale)))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x98 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x98 | dst | abase | 0x1 | 0x0 | offset |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT offset abase)) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x98 | dst | abase | 0x0 | 0x0 | offset |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp offset) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x80 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set dst (mem UQI optdisp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x80 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(set dst (mem UQI (add UINT optdisp (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x80 | dst | abase | 0x4 | scale | 0x0 | indx |
(set dst (mem UQI abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x80 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set dst (mem UQI (add UINT optdisp abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x80 | dst | abase | 0x7 | scale | 0x0 | indx |
(set dst (mem UQI (add SI abase (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x80 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(set dst (mem UQI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x80 | dst | abase | 0x1 | 0x0 | offset |
(set dst (mem UQI (add UINT offset abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x80 | dst | abase | 0x0 | 0x0 | offset |
(set dst (mem UQI offset))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x88 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(set dst (mem UHI optdisp))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x88 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(set dst (mem UHI (add UINT optdisp (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x88 | dst | abase | 0x4 | scale | 0x0 | indx |
(set dst (mem UHI abase))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x88 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(set dst (mem UHI (add UINT optdisp abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x88 | dst | abase | 0x7 | scale | 0x0 | indx |
(set dst (mem UHI (add SI abase (mul SI indx (sll SI 1 scale)))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x88 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(set dst (mem UHI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x88 | dst | abase | 0x1 | 0x0 | offset |
(set dst (mem UHI (add UINT offset abase)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x88 | dst | abase | 0x0 | 0x0 | offset |
(set dst (mem UHI offset))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb0 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp optdisp) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb0 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp (mul SI indx (sll SI 1 scale)))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb0 | dst | abase | 0x4 | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp abase) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb0 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp abase)) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb0 | dst | abase | 0x7 | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add SI abase (mul SI indx (sll SI 1 scale)))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb0 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xb0 | dst | abase | 0x1 | 0x0 | offset |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT offset abase)) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xb0 | dst | abase | 0x0 | 0x0 | offset |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp offset) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))) (set (reg SI h-gr (add INT (index-of dst) 3)) (mem WI (add SI temp 12))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa0 | optdisp | dst | abase | 0xc | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp optdisp) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa0 | optdisp | dst | abase | 0xe | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp (mul SI indx (sll SI 1 scale)))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa0 | dst | abase | 0x4 | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp abase) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa0 | optdisp | dst | abase | 0xd | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp abase)) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa0 | dst | abase | 0x7 | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add SI abase (mul SI indx (sll SI 1 scale)))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa0 | optdisp | dst | abase | 0xf | scale | 0x0 | indx |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xa0 | dst | abase | 0x1 | 0x0 | offset |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp (add UINT offset abase)) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xa0 | dst | abase | 0x0 | 0x0 | offset |
(sequence ((WI temp) (SI dregno)) (set dregno f-srcdst) (set temp offset) (set dst (mem WI temp)) (set (reg SI h-gr (add INT (index-of dst) 1)) (mem WI (add SI temp 4))) (set (reg SI h-gr (add INT (index-of dst) 2)) (mem WI (add SI temp 8))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x64 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x5 | 0x0 | src1 |
(set dst src2)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x65 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x5 | 0x0 | src1 |
(set dst src2)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5c | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xc | 0x0 | src1 |
(set dst src1)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5c | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xc | 0x0 | lit1 |
(set dst lit1)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5d | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xc | 0x0 | src1 |
(sequence ((SI dregno) (SI sregno)) (set dregno f-srcdst) (set sregno f-src1) (set dst src1) (set (reg SI h-gr (add INT (index-of dst) 1)) (reg SI h-gr (add INT (index-of src1) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5d | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xc | 0x0 | lit1 |
(sequence ((SI dregno)) (set dregno f-srcdst) (set dst lit1) (set (reg SI h-gr (add INT (index-of dst) 1)) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5f | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xc | 0x0 | src1 |
(sequence ((SI dregno) (SI sregno)) (set dregno f-srcdst) (set sregno f-src1) (set dst src1) (set (reg SI h-gr (add INT (index-of dst) 1)) (reg SI h-gr (add INT (index-of src1) 1))) (set (reg SI h-gr (add INT (index-of dst) 2)) (reg SI h-gr (add INT (index-of src1) 2))) (set (reg SI h-gr (add INT (index-of dst) 3)) (reg SI h-gr (add INT (index-of src1) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5f | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xc | 0x0 | lit1 |
(sequence ((SI dregno)) (set dregno f-srcdst) (set dst lit1) (set (reg SI h-gr (add INT (index-of dst) 1)) 0) (set (reg SI h-gr (add INT (index-of dst) 2)) 0) (set (reg SI h-gr (add INT (index-of dst) 3)) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5e | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xc | 0x0 | src1 |
(sequence ((SI dregno) (SI sregno)) (set dregno f-srcdst) (set sregno f-src1) (set dst src1) (set (reg SI h-gr (add INT (index-of dst) 1)) (reg SI h-gr (add INT (index-of src1) 1))) (set (reg SI h-gr (add INT (index-of dst) 2)) (reg SI h-gr (add INT (index-of src1) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x5e | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xc | 0x0 | lit1 |
(sequence ((SI dregno)) (set dregno f-srcdst) (set dst lit1) (set (reg SI h-gr (add INT (index-of dst) 1)) 0) (set (reg SI h-gr (add INT (index-of dst) 2)) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 | src1 |
(set dst (mul SI src1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x1 | 0x0 | lit1 |
(set dst (mul UINT lit1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x1 | 0x0 | src1 |
(set dst (mul SI src1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x1 | 0x0 | lit1 |
(set dst (mul UINT lit1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (and SI (inv SI src2) (inv SI src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (and SI (inv SI src2) (inv UINT lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (and UINT (inv UINT lit2) (inv SI src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (and UINT (inv UINT lit2) (inv UINT lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xa | 0x0 | src1 |
(set dst (inv SI src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xa | 0x0 | lit1 |
(set dst (inv UINT lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xa | 0x0 | src1 |
(set dst (inv SI src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xa | 0x0 | lit1 |
(set dst (inv UINT lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x4 | 0x0 | src1 |
(set dst (and SI (inv SI src2) src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x4 | 0x0 | lit1 |
(set dst (and SI (inv SI src2) lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x4 | 0x0 | src1 |
(set dst (and UINT (inv UINT lit2) src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x4 | 0x0 | lit1 |
(set dst (and UINT (inv UINT lit2) lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | src1 |
(set dst (xor SI (sll SI 1 src1) src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x0 | 0x0 | lit1 |
(set dst (xor SI (sll SI 1 lit1) src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x0 | 0x0 | src1 |
(set dst (xor SI (sll SI 1 src1) lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x0 | 0x0 | lit1 |
(set dst (xor SI (sll SI 1 lit1) lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x7 | 0x0 | src1 |
(set dst (or SI src1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x7 | 0x0 | lit1 |
(set dst (or UINT lit1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x7 | 0x0 | src1 |
(set dst (or SI src1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x7 | 0x0 | lit1 |
(set dst (or UINT lit1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xb | 0x0 | src1 |
(set dst (or SI src2 (inv SI src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (or SI src2 (inv UINT lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xb | 0x0 | src1 |
(set dst (or UINT lit2 (inv SI src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (or UINT lit2 (inv UINT lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (mod SI src2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (mod SI src2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (mod UINT lit2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x74 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (mod UINT lit2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (umod SI src2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (umod SI src2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (umod UINT lit2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x70 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (umod UINT lit2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-ctrl-disp | f-ctrl-zero |
0xa | ctrl_disp | 0x0 |
(sequence () (set (reg SI h-gr 31) (reg SI h-gr 0)) (set-quiet (reg SI h-gr 0) (mem WI (add SI (reg SI h-gr 31) 0))) (set-quiet (reg SI h-gr 1) (mem WI (add SI (reg SI h-gr 31) 4))) (set-quiet (reg SI h-gr 2) (mem WI (add SI (reg SI h-gr 31) 8))) (set-quiet (reg SI h-gr 3) (mem WI (add SI (reg SI h-gr 31) 12))) (set-quiet (reg SI h-gr 4) (mem WI (add SI (reg SI h-gr 31) 16))) (set-quiet (reg SI h-gr 5) (mem WI (add SI (reg SI h-gr 31) 20))) (set-quiet (reg SI h-gr 6) (mem WI (add SI (reg SI h-gr 31) 24))) (set-quiet (reg SI h-gr 7) (mem WI (add SI (reg SI h-gr 31) 28))) (set-quiet (reg SI h-gr 8) (mem WI (add SI (reg SI h-gr 31) 32))) (set-quiet (reg SI h-gr 9) (mem WI (add SI (reg SI h-gr 31) 36))) (set-quiet (reg SI h-gr 10) (mem WI (add SI (reg SI h-gr 31) 40))) (set-quiet (reg SI h-gr 11) (mem WI (add SI (reg SI h-gr 31) 44))) (set-quiet (reg SI h-gr 12) (mem WI (add SI (reg SI h-gr 31) 48))) (set-quiet (reg SI h-gr 13) (mem WI (add SI (reg SI h-gr 31) 52))) (set-quiet (reg SI h-gr 14) (mem WI (add SI (reg SI h-gr 31) 56))) (set-quiet (reg SI h-gr 15) (mem WI (add SI (reg SI h-gr 31) 60))) (set pc (reg SI h-gr 2)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x3 | 0x0 | src1 |
(set dst (or SI (sll SI 1 src1) src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x3 | 0x0 | lit1 |
(set dst (or SI (sll SI 1 lit1) src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x3 | 0x0 | src1 |
(set dst (or SI (sll SI 1 src1) lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x3 | 0x0 | lit1 |
(set dst (or SI (sll SI 1 lit1) lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xe | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) 0) (else sll SI src2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xe | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) 0) (else sll SI src2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xe | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) 0) (else sll UINT lit2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xe | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) 0) (else sll UINT lit2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xc | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) 0) (else sll SI src2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xc | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) 0) (else sll SI src2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xc | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) 0) (else sll UINT lit2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xc | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) 0) (else sll UINT lit2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x0 | 0xb | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) (sra SI src2 31)) (else sra SI src2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) (sra SI src2 31)) (else sra SI src2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0xb | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) (sra UINT lit2 31)) (else sra UINT lit2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0xb | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) (sra UINT lit2 31)) (else sra UINT lit2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) 0) (else srl SI src2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) 0) (else srl SI src2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x8 | 0x0 | src1 |
(set dst (cond WI ((geu src1 32) 0) (else srl UINT lit2 src1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x8 | 0x0 | lit1 |
(set dst (cond WI ((geu lit1 32) 0) (else srl UINT lit2 lit1)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x92 | optdisp | st_src | abase | 0xc | scale | 0x0 | indx |
(set (mem WI optdisp) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x92 | optdisp | st_src | abase | 0xe | scale | 0x0 | indx |
(set (mem WI (add UINT optdisp (mul SI indx (sll SI 1 scale)))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x92 | st_src | abase | 0x4 | scale | 0x0 | indx |
(set (mem WI abase) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x92 | optdisp | st_src | abase | 0xd | scale | 0x0 | indx |
(set (mem WI (add UINT optdisp abase)) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x92 | st_src | abase | 0x7 | scale | 0x0 | indx |
(set (mem WI (add SI abase (mul SI indx (sll SI 1 scale)))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x92 | optdisp | st_src | abase | 0xf | scale | 0x0 | indx |
(set (mem WI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x92 | st_src | abase | 0x1 | 0x0 | offset |
(set (mem WI (add UINT offset abase)) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x92 | st_src | abase | 0x0 | 0x0 | offset |
(set (mem WI offset) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x9a | optdisp | st_src | abase | 0xc | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI optdisp) st_src) (set (mem WI (add UINT optdisp 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x9a | optdisp | st_src | abase | 0xe | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp (mul SI indx (sll SI 1 scale)))) st_src) (set (mem WI (add UINT (add UINT optdisp (mul SI indx (sll SI 1 scale))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x9a | st_src | abase | 0x4 | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI abase) st_src) (set (mem WI (add SI abase 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x9a | optdisp | st_src | abase | 0xd | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp abase)) st_src) (set (mem WI (add UINT (add UINT optdisp abase) 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x9a | st_src | abase | 0x7 | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add SI abase (mul SI indx (sll SI 1 scale)))) st_src) (set (mem WI (add SI (add SI abase (mul SI indx (sll SI 1 scale))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x9a | optdisp | st_src | abase | 0xf | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) st_src) (set (mem WI (add UINT (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x9a | st_src | abase | 0x1 | 0x0 | offset |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT offset abase)) st_src) (set (mem WI (add UINT (add UINT offset abase) 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x9a | st_src | abase | 0x0 | 0x0 | offset |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI offset) st_src) (set (mem WI (add UINT offset 4)) (reg SI h-gr (add INT (index-of st_src) 1))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x82 | optdisp | st_src | abase | 0xc | scale | 0x0 | indx |
(set (mem QI optdisp) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x82 | optdisp | st_src | abase | 0xe | scale | 0x0 | indx |
(set (mem QI (add UINT optdisp (mul SI indx (sll SI 1 scale)))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x82 | st_src | abase | 0x4 | scale | 0x0 | indx |
(set (mem QI abase) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x82 | optdisp | st_src | abase | 0xd | scale | 0x0 | indx |
(set (mem QI (add UINT optdisp abase)) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x82 | st_src | abase | 0x7 | scale | 0x0 | indx |
(set (mem QI (add SI abase (mul SI indx (sll SI 1 scale)))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x82 | optdisp | st_src | abase | 0xf | scale | 0x0 | indx |
(set (mem QI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x82 | st_src | abase | 0x1 | 0x0 | offset |
(set (mem QI (add UINT offset abase)) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x82 | st_src | abase | 0x0 | 0x0 | offset |
(set (mem QI offset) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8a | optdisp | st_src | abase | 0xc | scale | 0x0 | indx |
(set (mem HI optdisp) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8a | optdisp | st_src | abase | 0xe | scale | 0x0 | indx |
(set (mem HI (add UINT optdisp (mul SI indx (sll SI 1 scale)))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8a | st_src | abase | 0x4 | scale | 0x0 | indx |
(set (mem HI abase) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8a | optdisp | st_src | abase | 0xd | scale | 0x0 | indx |
(set (mem HI (add UINT optdisp abase)) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8a | st_src | abase | 0x7 | scale | 0x0 | indx |
(set (mem HI (add SI abase (mul SI indx (sll SI 1 scale)))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0x8a | optdisp | st_src | abase | 0xf | scale | 0x0 | indx |
(set (mem HI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x8a | st_src | abase | 0x1 | 0x0 | offset |
(set (mem HI (add UINT offset abase)) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0x8a | st_src | abase | 0x0 | 0x0 | offset |
(set (mem HI offset) st_src)
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb2 | optdisp | st_src | abase | 0xc | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI optdisp) st_src) (set (mem WI (add UINT optdisp 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT optdisp 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add UINT optdisp 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb2 | optdisp | st_src | abase | 0xe | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp (mul SI indx (sll SI 1 scale)))) st_src) (set (mem WI (add UINT (add UINT optdisp (mul SI indx (sll SI 1 scale))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT optdisp (mul SI indx (sll SI 1 scale))) 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add UINT (add UINT optdisp (mul SI indx (sll SI 1 scale))) 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb2 | st_src | abase | 0x4 | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI abase) st_src) (set (mem WI (add SI abase 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add SI abase 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add SI abase 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb2 | optdisp | st_src | abase | 0xd | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp abase)) st_src) (set (mem WI (add UINT (add UINT optdisp abase) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT optdisp abase) 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add UINT (add UINT optdisp abase) 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb2 | st_src | abase | 0x7 | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add SI abase (mul SI indx (sll SI 1 scale)))) st_src) (set (mem WI (add SI (add SI abase (mul SI indx (sll SI 1 scale))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add SI (add SI abase (mul SI indx (sll SI 1 scale))) 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add SI (add SI abase (mul SI indx (sll SI 1 scale))) 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xb2 | optdisp | st_src | abase | 0xf | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) st_src) (set (mem WI (add UINT (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))) 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add UINT (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))) 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xb2 | st_src | abase | 0x1 | 0x0 | offset |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT offset abase)) st_src) (set (mem WI (add UINT (add UINT offset abase) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT offset abase) 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add UINT (add UINT offset abase) 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xb2 | st_src | abase | 0x0 | 0x0 | offset |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI offset) st_src) (set (mem WI (add UINT offset 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT offset 8)) (reg SI h-gr (add INT (index-of st_src) 2))) (set (mem WI (add UINT offset 12)) (reg SI h-gr (add INT (index-of st_src) 3))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa2 | optdisp | st_src | abase | 0xc | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI optdisp) st_src) (set (mem WI (add UINT optdisp 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT optdisp 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa2 | optdisp | st_src | abase | 0xe | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp (mul SI indx (sll SI 1 scale)))) st_src) (set (mem WI (add UINT (add UINT optdisp (mul SI indx (sll SI 1 scale))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT optdisp (mul SI indx (sll SI 1 scale))) 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa2 | st_src | abase | 0x4 | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI abase) st_src) (set (mem WI (add SI abase 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add SI abase 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa2 | optdisp | st_src | abase | 0xd | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp abase)) st_src) (set (mem WI (add UINT (add UINT optdisp abase) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT optdisp abase) 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 19 20 21 | 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa2 | st_src | abase | 0x7 | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add SI abase (mul SI indx (sll SI 1 scale)))) st_src) (set (mem WI (add SI (add SI abase (mul SI indx (sll SI 1 scale))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add SI (add SI abase (mul SI indx (sll SI 1 scale))) 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 | 40 41 42 43 44 | 45 46 47 48 49 | 50 51 52 53 | 54 55 56 | 57 58 | 59 60 61 62 63 |
f-opcode | f-optdisp | f-srcdst | f-abase | f-modeb | f-scale | f-zerob | f-index |
0xa2 | optdisp | st_src | abase | 0xf | scale | 0x0 | indx |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale))))) st_src) (set (mem WI (add UINT (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT optdisp (add SI abase (mul SI indx (sll SI 1 scale)))) 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xa2 | st_src | abase | 0x1 | 0x0 | offset |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI (add UINT offset abase)) st_src) (set (mem WI (add UINT (add UINT offset abase) 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT (add UINT offset abase) 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcode | f-srcdst | f-abase | f-modea | f-zeroa | f-offset |
0xa2 | st_src | abase | 0x0 | 0x0 | offset |
(sequence ((SI sregno)) (set sregno f-srcdst) (set (mem WI offset) st_src) (set (mem WI (add UINT offset 4)) (reg SI h-gr (add INT (index-of st_src) 1))) (set (mem WI (add UINT offset 8)) (reg SI h-gr (add INT (index-of st_src) 2))))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x2 | 0x0 | src1 |
(set dst (sub SI src2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x2 | 0x0 | lit1 |
(set dst (sub SI src2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x2 | 0x0 | src1 |
(set dst (sub UINT lit2 src1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x59 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x2 | 0x0 | lit1 |
(set dst (sub UINT lit2 lit1))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x22 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 2) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x21 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 1) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x23 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 3) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x24 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 4) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x26 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 6) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x25 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 5) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x20 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (eq (reg SI h-cc 0) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 20 21 22 23 24 25 26 27 28 29 | 30 31 |
f-opcode | f-br-src1 | f-br-src2 | f-br-m1 | f-br-disp | f-br-zero |
0x27 | br_src1 | br_src2 | 0x0 | br_disp | 0x0 |
(set br_src1 (ne (and SI (reg SI h-cc 0) 7) 0))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x9 | 0x0 | src1 |
(set dst (inv SI (xor SI src1 src2)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x9 | 0x0 | lit1 |
(set dst (inv UINT (xor UINT lit1 src2)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x9 | 0x0 | src1 |
(set dst (inv SI (xor SI src1 lit2)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x9 | 0x0 | lit1 |
(set dst (inv UINT (xor UINT lit1 lit2)))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x0 | 0x6 | 0x0 | src1 |
(set dst (xor SI src1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | src2 | 0x0 | 0x0 | 0x1 | 0x6 | 0x0 | lit1 |
(set dst (xor UINT lit1 src2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x0 | 0x6 | 0x0 | src1 |
(set dst (xor SI src1 lit2))
0 1 2 3 4 5 6 7 | 8 9 10 11 12 | 13 14 15 16 17 | 18 | 19 | 20 | 21 22 23 24 | 25 26 | 27 28 29 30 31 |
f-opcode | f-srcdst | f-src2 | f-m3 | f-m2 | f-m1 | f-opcode2 | f-zero | f-src1 |
0x58 | dst | lit2 | 0x0 | 0x1 | 0x1 | 0x6 | 0x0 | lit1 |
(set dst (xor UINT lit1 lit2))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/