31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x20 |
(set rd (add SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x20 |
(set rd-rs (add SI rt rd-rs))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x8 | rs | rt | lo16 |
(set rt (add SI rs (ext SI (trunc HI lo16))))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0x8 | rt-rs | lo16 |
(set rt-rs (add SI rt-rs (ext SI (trunc HI lo16))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x9 | rs | rt | lo16 |
(set rt (add SI rs (ext SI (trunc HI lo16))))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0x9 | rt-rs | lo16 |
(set rt-rs (add SI rt-rs (ext SI (trunc HI lo16))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x21 |
(set rd (add SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x21 |
(set rd-rs (add SI rd-rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x29 |
(sequence ((HI high) (HI low)) (set low (add HI (and HI rs 65535) (and HI rt 65535))) (set high (add HI (srl SI rs 16) (srl SI rt 16))) (set rd (or SI (sll SI high 16) low)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x29 |
(sequence ((HI high) (HI low)) (set low (add HI (and HI rd-rs 65535) (and HI rt 65535))) (set high (add HI (srl SI rd-rs 16) (srl SI rt 16))) (set rd-rs (or SI (sll SI high 16) low)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x24 |
(set rd (and SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x24 |
(set rd-rs (and SI rd-rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xc | rs | rt | lo16 |
(set rt (and SI rs (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0xc | rt-rs | lo16 |
(set rt-rs (and SI rt-rs (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x2c | rs | rt | lo16 |
(set rt (and SI rs (or INT 4294901760 (ext SI (trunc HI lo16)))))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0x2c | rt-rs | lo16 |
(set rt-rs (and SI rt-rs (or INT 4294901760 (ext SI (trunc HI lo16)))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x3f | rs | rt | hi16 |
(set rt (and SI rs (or UINT (sll UINT hi16 16) 65535)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x2f | rs | rt | hi16 |
(set rt (and SI rs (or UINT (sll UINT hi16 16) 65535)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0x3f | rt-rs | hi16 |
(set rt-rs (and SI rt-rs (or UINT (sll UINT hi16 16) 65535)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0x2f | rt-rs | hi16 |
(set rt-rs (and SI rt-rs (or UINT (sll UINT hi16 16) 65535)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | 0x0 | rd | 0x0 | 0x24 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1c | rs | bitnum | offset |
(if (and SI rs (sll INT 1 bitnum)) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x3c | rs | bitnum | offset |
(if (and SI rs (sll INT 1 bitnum)) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1e | rs | bitnum | offset |
(if (not SI (and SI rs (sll INT 1 bitnum))) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x3e | rs | bitnum | offset |
(if (not SI (and SI rs (sll INT 1 bitnum))) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1d | rs | rt | offset |
(if (and SI rs (sll INT 1 (and SI rt 31))) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x3d | rs | rt | offset |
(if (and SI rs (sll INT 1 (and SI rt 31))) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1f | rs | rt | offset |
(if (not SI (and SI rs (sll INT 1 (and SI rt 31)))) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x3f | rs | rt | offset |
(if (not SI (and SI rs (sll INT 1 (and SI rt 31)))) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x10 | 0x8 | 0x0 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x10 | 0x8 | 0x2 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x10 | 0x8 | 0x1 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x10 | 0x8 | 0x3 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x13 | 0x8 | 0x0 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x13 | 0x8 | 0x2 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x13 | 0x8 | 0x1 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x13 | 0x8 | 0x3 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0xc | offset |
(delay VOID 1 (set pc offset))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x6 | offset |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x4 | rs | rt | offset |
(if (eq rs rt) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x14 | rs | rt | offset |
(if (eq rs rt) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x1 | offset |
(if (ge rs 0) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x11 | offset |
(if (ge rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x13 | offset |
(if (ge rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x3 | offset |
(if (ge rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x7 | rs | 0x0 | offset |
(if (gt rs 0) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x5 | offset |
(if (gt rs 0) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x15 | offset |
(if (gt rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x17 | offset |
(if (gt rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x17 | rs | 0x0 | offset |
(if (gt rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x7 | offset |
(if (gt rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x6 | rs | 0x0 | offset |
(if (le rs 0) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x4 | offset |
(if (le rs 0) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x14 | offset |
(if (le rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x16 | offset |
(if (le rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x16 | rs | 0x0 | offset |
(if (le rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x6 | offset |
(if (le rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x0 | offset |
(if (lt rs 0) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x10 | offset |
(if (lt rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x12 | offset |
(if (lt rs 0) (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (delay VOID 1 (set pc offset))) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x2 | offset |
(if (lt rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x2d | rs | rt | offset |
(sequence ((BI branch?)) (set branch? 0) (if (eq (and SI rs 255) (and SI rt 255)) (set branch? 1)) (if (eq (and SI rs 65280) (and SI rt 65280)) (set branch? 1)) (if (eq (and SI rs 16711680) (and SI rt 16711680)) (set branch? 1)) (if (eq (and SI rs 4278190080) (and SI rt 4278190080)) (set branch? 1)) (if branch? (delay VOID 1 (set pc offset))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x6 | rs | rt | offset |
(sequence ((BI branch?)) (set branch? 0) (if (eq (and SI rs 255) (and SI rt 255)) (set branch? 1)) (if (eq (and SI rs 65280) (and SI rt 65280)) (set branch? 1)) (if (eq (and SI rs 16711680) (and SI rt 16711680)) (set branch? 1)) (if (eq (and SI rs 4278190080) (and SI rt 4278190080)) (set branch? 1)) (if branch? (delay VOID 1 (set pc offset))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x18 | rs | rt | offset |
(if (eq (and SI rs 255) (and SI rt 255)) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x19 | rs | rt | offset |
(if (eq (and SI rs 65280) (and SI rt 65280)) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1a | rs | rt | offset |
(if (eq (and SI rs 16711680) (and SI rt 16711680)) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1b | rs | rt | offset |
(if (eq (and SI rs 4278190080) (and SI rt 4278190080)) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x16 | rs | rt | offset |
(sequence ((BI branch?)) (set branch? 0) (if (eq (and SI rs 255) (and SI rt 255)) (set branch? 1)) (if (eq (and SI rs 65280) (and SI rt 65280)) (set branch? 1)) (if (eq (and SI rs 16711680) (and SI rt 16711680)) (set branch? 1)) (if (eq (and SI rs 4278190080) (and SI rt 4278190080)) (set branch? 1)) (if branch? (delay VOID 1 (set pc offset)) (skip VOID 1)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x5 | rs | rt | offset |
(if (ne rs rt) (delay VOID 1 (set pc offset)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x15 | rs | rt | offset |
(if (ne rs rt) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0xd |
(c-call VOID "do_break" pc)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x8 | offset |
(if (gt rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-offset |
0x1 | rs | 0x9 | offset |
(if (gt rs 0) (delay VOID 1 (set pc offset)) (skip VOID 1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op-10 | f-cam-z | f-cam-y |
0x13 | 0x0 | rt | rd | 0x12 | cam-z | cam-y |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op-10 | f-cam-z | f-cam-y |
0x13 | 0x0 | rt | rd | 0x13 | cam-z | cam-y |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op-10 | f-cam-z | f-cam-y |
0x13 | 0x0 | rt | rd | 0x10 | cam-z | cam-y |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 | 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op-10 | f-cam-z | f-cam-y |
0x13 | 0x0 | rt | rd | 0x11 | cam-z | cam-y |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x10 | 0x2 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x11 | 0x2 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x12 | 0x2 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x13 | 0x2 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x9 | rt | rd | 0x0 | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | 0x0 | rd | 0x0 | 0x26 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x15 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 | 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-cm-4func | f-cm-3z |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x4 | cm-3z |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 | 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-cm-3func | f-cm-4z |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x6 | cm-4z |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x1d |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 | 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-cm-4func | f-cm-3z |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x6 | cm-3z |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 | 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-cm-3func | f-cm-4z |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x7 | cm-4z |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x26 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x2b |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x23 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x2a |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x2 | 0x30 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x21 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x24 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x2 | 0x20 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x38 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x29 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x2c |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x28 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x22 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x5 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x10 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x1 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x4 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x14 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x18 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0x9 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x2 | 0xc |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x1c |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-cp-grp | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2 | 0x8 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | 0x0 | rd | 0x0 | 0x2c |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x2e |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x14 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x15 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | 0x0 | 0x0 | 0x2 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x10 | 0x6 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x11 | 0x6 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x12 | 0x6 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x13 | 0x6 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | 0x0 | rd | 0x0 | 0x22 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x21 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | 0x0 | rd | 0x0 | 0x23 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0xc |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0xd |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | 0x0 | rd | 0x0 | 0x25 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rsrvd | f-jtarg |
0x2 | 0x0 | jmptarg |
(delay VOID 1 (set pc jmptarg))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rsrvd | f-jtarg |
0x3 | 0x0 | jmptarg |
(delay VOID 1 (sequence () (set (reg SI h-gr 31) (add USI pc 8)) (set pc jmptarg)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-jtarg |
0x3 | 0x0 | rt | jmptarg |
(delay VOID 1 (sequence () (set rt (add USI pc 8)) (set pc jmptarg)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-jtarg |
0x3 | 0x0 | 0x1f | jmptarg |
(delay VOID 1 (sequence () (set rt (add USI pc 8)) (set pc jmptarg)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | 0x0 | rd | 0x0 | 0x9 |
(delay VOID 1 (sequence () (set rd (add USI pc 8)) (set pc rs)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | 0x0 | 0x0 | 0x0 | 0xa |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-jtarg |
0x2 | 0x0 | 0x0 | jmptarg |
(delay VOID 1 (set pc jmptarg))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | 0x0 | 0x0 | 0x0 | 0x8 |
(delay VOID 1 (set pc rs))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x20 | base | rt | lo16 |
(set rt (ext WI (mem QI (add SI base (ext SI (trunc HI lo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x24 | base | rt | lo16 |
(set rt (zext WI (mem QI (add SI base (ext SI (trunc HI lo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x30 | base | rt | lo16 |
(sequence ((SI addr)) (set addr (and SI (add SI base lo16) (inv INT 3))) (set (reg SI h-gr (add UINT f-rt 1)) (mem SI addr)) (set rt (mem SI (add SI addr 4))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x21 | base | rt | lo16 |
(set rt (ext WI (mem HI (add SI base (ext SI (trunc HI lo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x25 | base | rt | lo16 |
(set rt (zext WI (mem HI (add SI base (ext SI (trunc HI lo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x1 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x3 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x7 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0xb |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0xf |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xf | 0x0 | rt | hi16 |
(set rt (sll UINT hi16 16))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x8 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | 0x0 | 0x0 | 0x4 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x2 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x6 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0xa |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0xe |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x1 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x5 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | 0x0 | 0x0 | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x23 | base | rt | lo16 |
(set rt (mem SI (add SI base (ext SI (trunc HI lo16)))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x20 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x10 | 0x0 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x11 | 0x0 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x12 | 0x0 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x13 | 0x0 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 | 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10 | f-mask | f-func |
0x0 | rs | rt | rd | 0x0 | mask | 0x2d |
(sequence ((SI temp)) (if (not UINT (and UINT mask (sll INT 1 0))) (set temp (and SI rs 255)) (set temp (and SI rt 255))) (if (not UINT (and UINT mask (sll INT 1 1))) (set temp (or SI temp (and SI rs 65280))) (set temp (or SI temp (and SI rt 65280)))) (if (not UINT (and UINT mask (sll INT 1 2))) (set temp (or SI temp (and SI rs 16711680))) (set temp (or SI temp (and SI rt 16711680)))) (if (not UINT (and UINT mask (sll INT 1 3))) (set temp (or SI temp (and SI rs 4278190080))) (set temp (or SI temp (and SI rt 4278190080)))) (set rd temp))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 | 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-10 | f-mask | f-func |
0x0 | rt | rd-rs | 0x0 | mask | 0x2d |
(sequence ((SI temp)) (if (not UINT (and UINT mask (sll INT 1 0))) (set temp (and SI rd-rs 255)) (set temp (and SI rt 255))) (if (not UINT (and UINT mask (sll INT 1 1))) (set temp (or SI temp (and SI rd-rs 65280))) (set temp (or SI temp (and SI rt 65280)))) (if (not UINT (and UINT mask (sll INT 1 2))) (set temp (or SI temp (and SI rd-rs 16711680))) (set temp (or SI temp (and SI rt 16711680)))) (if (not UINT (and UINT mask (sll INT 1 3))) (set temp (or SI temp (and SI rd-rs 4278190080))) (set temp (or SI temp (and SI rt 4278190080)))) (set rd-rs temp))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-maskq10 | f-func |
0x0 | rs | rt | rd | maskq10 | 0x2d |
(sequence ((SI temp)) (if (not UINT (and UINT mask (sll INT 1 0))) (set temp (and SI rs 255)) (set temp (and SI rt 255))) (if (not UINT (and UINT mask (sll INT 1 1))) (set temp (or SI temp (and SI rs 65280))) (set temp (or SI temp (and SI rt 65280)))) (if (not UINT (and UINT mask (sll INT 1 2))) (set temp (or SI temp (and SI rs 16711680))) (set temp (or SI temp (and SI rt 16711680)))) (if (not UINT (and UINT mask (sll INT 1 3))) (set temp (or SI temp (and SI rs 4278190080))) (set temp (or SI temp (and SI rt 4278190080)))) (set rd temp))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-maskq10 | f-func |
0x0 | rt | rd-rs | maskq10 | 0x2d |
(sequence ((SI temp)) (if (not UINT (and UINT mask (sll INT 1 0))) (set temp (and SI rd-rs 255)) (set temp (and SI rt 255))) (if (not UINT (and UINT mask (sll INT 1 1))) (set temp (or SI temp (and SI rd-rs 65280))) (set temp (or SI temp (and SI rt 65280)))) (if (not UINT (and UINT mask (sll INT 1 2))) (set temp (or SI temp (and SI rd-rs 16711680))) (set temp (or SI temp (and SI rt 16711680)))) (if (not UINT (and UINT mask (sll INT 1 3))) (set temp (or SI temp (and SI rd-rs 4278190080))) (set temp (or SI temp (and SI rt 4278190080)))) (set rd-rs temp))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x10 | 0x4 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x11 | 0x4 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x12 | 0x4 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-10-11 |
0x13 | 0x4 | rt | rd | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x27 |
(set rd (inv SI (or SI rs rt)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x27 |
(set rd-rs (inv SI (or SI rd-rs rt)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x25 |
(set rd (or SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x25 |
(set rd-rs (or SI rd-rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xd | rs | rt | lo16 |
(set rt (or SI rs (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0xd | rt-rs | lo16 |
(set rt-rs (or SI rt-rs (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x2f | rs | rt | hi16 |
(set rt (or SI rs (sll UINT hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xf | rs | rt | hi16 |
(set rt (or SI rs (sll UINT hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0x2f | rt-rs | hi16 |
(set rt-rs (or SI rt-rs (sll UINT hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0xf | rt-rs | hi16 |
(set rt-rs (or SI rt-rs (sll UINT hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x7 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x28 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2b |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x2a |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x29 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x12 | rs | rt | rd | 0x0 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x12 | rs | rt | rd | 0x3 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x12 | rs | rt | rd | 0x2 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x12 | rs | rt | rd | 0x1 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x1d | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x1f | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 | 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-5 | f-maskl |
0x27 | maskr | rt | rd | shamt | 0x0 | maskl |
(sequence () (set rd (ror SI rt shamt)) (set rd (and SI rd (srl INT 4294967295 maskl))) (set rd (and SI rd (sll INT 4294967295 maskr))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x4 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x8 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x9 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0xa |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x13 | rs | rt | rd | 0x2 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x13 | rs | rt | rd | 0x3 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x13 | rs | rt | rd | 0x1 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x18 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x1a | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 | 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-25 | f-24-19 | f-func |
0x10 | 0x1 | 0x0 | 0x10 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x6 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x1c | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x1e | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x28 | base | rt | lo16 |
(set (mem QI (add SI base (ext SI (trunc HI lo16)))) (and QI rt 255))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x38 | base | rt | lo16 |
(sequence ((SI addr)) (set addr (and SI (add SI base lo16) (inv INT 3))) (set (mem SI (add SI addr 4)) rt) (set (mem SI addr) (reg SI h-gr (add UINT f-rt 1))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x29 | base | rt | lo16 |
(set (mem HI (add SI base (ext SI (trunc HI lo16)))) (and HI rt 65535))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-excode | f-func |
0x0 | execode | 0xe |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | 0x0 | rt | rd | shamt | 0x0 |
(set rd (sll SI rt shamt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x4 |
(set rd (sll SI rt (and SI rs 31)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rd-rt | f-shamt | f-func |
0x0 | rs | rd-rt | 0x0 | 0x4 |
(set rd-rt (sll SI rd-rt (and SI rs 31)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | shamt | 0x1 |
(set rd (and SI (sll SI rt shamt) (srl INT 4294967295 rs)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rd-rt | f-shamt | f-func |
0x0 | rs | rd-rt | shamt | 0x1 |
(set rd-rt (and SI (sll SI rd-rt shamt) (srl INT 4294967295 rs)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x2a |
(if (lt rs rt) (set rd 1) (set rd 0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x2a |
(if (lt rd-rs rt) (set rd-rs 1) (set rd-rs 0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xa | rs | rt | imm |
(if (lt rs (ext SI (trunc HI imm))) (set rt 1) (set rt 0))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0xa | rt-rs | imm |
(if (lt rt-rs (ext SI (trunc HI imm))) (set rt-rs 1) (set rt-rs 0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xb | rs | rt | imm |
(if (ltu rs (ext SI (trunc HI imm))) (set rt 1) (set rt 0))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0xb | rt-rs | imm |
(if (ltu rt-rs (ext SI (trunc HI imm))) (set rt-rs 1) (set rt-rs 0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x2b |
(if (ltu rs rt) (set rd 1) (set rd 0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x2b |
(if (ltu rd-rs rt) (set rd-rs 1) (set rd-rs 0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | 0x0 | rt | rd | shamt | 0x3 |
(set rd (sra SI rt shamt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rd-rt | f-shamt | f-func |
0x0 | 0x0 | rd-rt | shamt | 0x3 |
(set rd-rt (sra SI rd-rt shamt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x7 |
(set rd (sra SI rt (and SI rs 31)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rd-rt | f-shamt | f-func |
0x0 | rs | rd-rt | 0x0 | 0x7 |
(set rd-rt (sra SI rd-rt (and SI rs 31)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | 0x0 | rt | rd | shamt | 0x2 |
(set rd (srl SI rt shamt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x6 |
(set rd (srl SI rt (and SI rs 31)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rd-rt | f-shamt | f-func |
0x0 | rs | rd-rt | 0x0 | 0x6 |
(set rd-rt (srl SI rd-rt (and SI rs 31)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | shamt | 0x5 |
(set rd (and SI (srl SI rt shamt) (sll INT 4294967295 rs)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rd-rt | f-shamt | f-func |
0x0 | rs | rd-rt | shamt | 0x5 |
(set rd-rt (and SI (srl SI rd-rt shamt) (sll INT 4294967295 rs)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | 0x0 | 0x0 | 0x10 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | 0x0 | 0x0 | 0x14 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | 0x0 | 0x0 | 0x16 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x11 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x12 | 0x1 | rt | rd | 0x0 | 0x15 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x22 |
(set rd (sub SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x22 |
(set rd-rs (sub SI rd-rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x23 |
(set rd (sub SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x23 |
(set rd-rs (sub SI rd-rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0x2b | base | rt | lo16 |
(set (mem SI (add SI base (ext SI (trunc HI lo16)))) rt)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x4 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x5 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x6 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x7 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-excode | f-func |
0x0 | execode | 0xc |
(c-call VOID "do_syscall")
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | 0x0 | 0x0 | 0x0 | 0x8 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | 0x0 | 0x0 | 0x0 | 0x9 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | 0x0 | 0x0 | 0xa |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | 0x0 | rd | 0x0 | 0x27 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x0 | rt | rd | 0x0 | 0x3 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x0 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x10 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x12 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | rs | rt | rd | 0x0 | 0x11 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x13 | rs | rt | rd | 0x6 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x13 | rs | rt | rd | 0x5 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 | 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-cp-op | f-bytecount |
0x13 | rs | rt | rd | 0x7 | bytecount |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x10 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x11 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x12 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x13 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x1 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x2 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x14 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x15 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x16 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-count | f-index |
0x13 | 0x17 | rt | count | _index |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x13 | 0x1 | rt | rd | 0x0 | 0x3 |
(nop)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | rs | rt | rd | 0x0 | 0x26 |
(set rd (xor SI rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rt | f-rd-rs | f-shamt | f-func |
0x0 | rt | rd-rs | 0x0 | 0x26 |
(set rd-rs (xor SI rd-rs rt))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-imm |
0xe | rs | rt | lo16 |
(set rt (xor SI rs (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-rt-rs | f-imm |
0xe | rt-rs | lo16 |
(set rt-rs (xor SI rt-rs (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 | 5 4 3 2 1 0 |
f-opcode | f-rs | f-rt | f-rd | f-shamt | f-func |
0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0xe |
(nop)
((emit lb rt lo16 (base 0)))
((emit lbu rt lo16 (base 0)))
((emit ldw rt lo16 (base 0)))
((emit lh rt lo16 (base 0)))
((emit ori (rt 0) rs imm))
((emit lw rt lo16 (base 0)))
((emit addi rt rs lo16))
((emit addiu rt rs lo16))
((emit andi rt rs lo16))
((emit avail (f-rd 0)))
((emit cam144 rd rt cam-z (f-cam-y 0)))
((emit cam288 rd rt cam-z (f-cam-y 0)))
((emit cam36 rd rt cam-z (f-cam-y 0)))
((emit cam72 rd rt cam-z (f-cam-y 0)))
((emit cm128ria2 (f-rd 0) rs rt))
((emit cm128ria3 (f-rd 0) rs rt cm-3z))
((emit cm128ria4 (f-rd 0) rs rt cm-4z))
((emit cm128sia2 (f-rd 0) rs rt))
((emit cm128sia3 (f-rd 0) rs rt cm-3z))
((emit cm128sia4 (f-rd 0) rs rt cm-4z))
((emit cm32and (f-rd 0) rs rt))
((emit cm32andn (f-rd 0) rs rt))
((emit cm32or (f-rd 0) rs rt))
((emit cm32or (f-rd 0) rs rt))
((emit cm32ra (f-rd 0) rs rt))
((emit cm32rd (f-rd 0) rt))
((emit cm32ra rd (f-rs 0) rt))
((emit cm32ri (f-rd 0) rt))
((emit cm32rs (f-rd 0) rs rt))
((emit cm32sa (f-rd 0) rs rt))
((emit cm32sd (f-rd 0) rt))
((emit cm32si (f-rd 0) rt))
((emit cm32ss (f-rd 0) rs rt))
((emit cm32xor (f-rd 0) rs rt))
((emit cm64clr (f-rd 0) rt))
((emit cm64ra (f-rd 0) rs rt))
((emit cm64rd (f-rd 0) rt))
((emit cm64ra rd (f-rs 0) rt))
((emit cm64ri (f-rd 0) rt))
((emit cm64ria2 (f-rd 0) rs rt))
((emit cm64rs (f-rd 0) rs rt))
((emit cm64sa (f-rd 0) rs rt))
((emit cm64sd (f-rd 0) rt))
((emit cm64si (f-rd 0) rt))
((emit cm64sia2 (f-rd 0) rs rt))
((emit cm64ss (f-rd 0) rs rt))
((emit cmphdr (f-rd 0)))
((emit dbd rd (f-rs 0) rt))
((emit dpwt (f-rd 0) rs))
((emit free (f-rd 0) rs))
((emit jr rs))
((emit lock (f-rd 0) rt))
((emit ori rt rs lo16))
((emit pkrla (f-rd 0) rs rt))
((emit pkrlac (f-rd 0) rs rt))
((emit pkrlah (f-rd 0) rs rt))
((emit pkrlau (f-rd 0) rs rt))
((emit pkrli (f-rd 0) rs rt bytecount))
((emit pkrlic (f-rd 0) rs rt bytecount))
((emit pkrlih (f-rd 0) rs rt bytecount))
((emit pkrliu (f-rd 0) rs rt bytecount))
((emit rba (f-rd 0) rs rt))
((emit rbal (f-rd 0) rs rt))
((emit rbar (f-rd 0) rs rt))
((emit rbi (f-rd 0) rs rt bytecount))
((emit rbil (f-rd 0) rs rt bytecount))
((emit rbir (f-rd 0) rs rt bytecount))
((emit sllv rd rt rs))
((emit slti rt rs imm))
((emit sltiu rt rs imm))
((emit srav rd rt rs))
((emit srlv rd rt rs))
((emit addiu rt rs mlo16))
((emit addiu rt rs mlo16))
((emit swwr (f-rd 0) rs rt))
((emit swwru (f-rd 0) rs rt))
((emit tstod (f-rd 0) rs))
((emit unlk (f-rd 0) rt))
((emit wba (f-rd 0) rs rt))
((emit wbac (f-rd 0) rs rt))
((emit wbau (f-rd 0) rs rt))
((emit wbi (f-rd 0) rs rt bytecount))
((emit wbic (f-rd 0) rs rt bytecount))
((emit wbiu (f-rd 0) rs rt bytecount))
((emit xori rt rs lo16))
((emit dbd (f-rd 0) (f-rs 0) rt))
((emit or rd (rs 0) rt))
((emit sll (rd 0) (rt 0) (shamt 0)))
((emit nor rd (rs 0) rt))
((emit sb rt lo16 (base 0)))
((emit sdw rt lo16 (base 0)))
((emit sh rt lo16 (base 0)))
((emit addiu rt rs mlo16))
((emit sw rt lo16 (base 0)))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/