Instructions

Instructions for each machine:

iq2000 MEM - Memory


iq2000 ALU - ALU


iq2000 BR - Branch


iq2000 iq2000 - IQ2000 packet processing engine


iq10 MEM - Memory


iq10 ALU - ALU


iq10 BR - Branch


iq10 iq10 - IQ10 coprocessor


Individual instructions descriptions


add - add registers

add2 - add registers

addi - add immediate

addi2 - add immediate

addiu - add immediate unsigned

addiu2 - add immediate unsigned

addu - add unsigned

addu2 - add unsigned

ado16 - add 16, ones complement

ado162 - add 16, ones complement

and - and register

and2 - and register

andi - and immediate

andi2 - and immediate

andoi - and ones immediate

andoi2 - and ones immediate

andoui - and upper ones immediate

andoui-q10 - iq10 and upper ones immediate

andoui2 - and upper ones immediate

andoui2-q10 - iq10 and upper ones immediate

avail - Mark Header Buffer Available

bbi - branch bit immediate

bbil - branch bit immediate likely

bbin - branch bit immediate negated

bbinl - branch bit immediate negated likely

bbv - branch bit variable

bbvl - branch bit variable likely

bbvn - branch bit variable negated

bbvnl - branch bit variable negated likely

bc0f - branch if copro 0 condition false

bc0fl - branch if copro 0 condition false likely

bc0t - branch if copro 0 condition true

bc0tl - branch if copro 0 condition true likely

bc3f - branch if copro 3 condition false

bc3fl - branch if copro 3 condition false likely

bc3t - branch if copro 3 condition true

bc3tl - branch if copro 3 condition true likely

bctx - branch if the current context == instruction[21]

bctxt - branch and switch context

beq - branch if equal

beql - branch if equal likely

bgez - branch if greater than or equal to zero

bgezal - branch if greater than or equal to zero and link

bgezall - branch if greater than equal to zero and link likely

bgezl - branch if greater or equal to zero likely

bgtz - branch if greater than zero

bgtz-q10 - branch if greater than zero

bgtzal - branch if greater than zero and link

bgtzall - branch if greater than zero and link likely

bgtzl - branch if greater than zero likely

bgtzl-q10 - branch if greater than zero likely

blez - branch if less than or equal to zero

blez-q10 - branch if less than or equal to zero

blezal - branch if less than or equal to zero and link

blezall - branch if less than or equal to zero and link likely

blezl - branch if less than or equal to zero likely

blezl-q10 - branch if less than or equal to zero likely

bltz - branch if less than zero

bltzal - branch if less than zero and link

bltzall - branch if less than zero and link likely

bltzl - branch if less than zero likely

bmb - branch if matching byte-lane

bmb-q10 - branch if matching byte-lane

bmb0 - branch if matching byte-lane 0

bmb1 - branch if matching byte-lane 1

bmb2 - branch if matching byte-lane 2

bmb3 - branch if matching byte-lane 3

bmbl - branch if matching byte-lane likely

bne - branch if not equal

bnel - branch if not equal likely

break - breakpoint

bri - branch if register invalid

brv - branch if register invalid

cam144 - CAM Access in 144-bit Mode

cam288 - CAM Access in 288-bit Mode

cam36 - CAM Access in 36-bit Mode

cam72 - CAM Access in 72-bit Mode

cfc - copy from coprocessor control register

cfc0 - control from coprocessor 0

cfc1 - control from coprocessor 1

cfc2 - control from coprocessor 2

cfc3 - control from coprocessor 3

chkhdr - check header

chkhdrq10 -

cm128ria2 - Counter Manager 128-bit 64/64 Rolling Increment/Add

cm128ria3 - Counter Manager 128-bit 32/32/64 Rolling Increment/Add

cm128ria4 - Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add

cm128sia2 - Counter Manager 128-bit 64/64 Saturating Inc/Add

cm128sia3 - Counter Manager 128-bit 32/32/64 Saturating Inc/Add

cm128sia4 - Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add

cm128vsa - Counter Manager Continuous State Dual Leaky Token Bucket Policing

cm32and - Counter Manager And

cm32andn - Counter Manager And With Inverse

cm32or - Counter Manager Or

cm32ra - Counter Manager 32-bit Rolling Add

cm32rd - Counter Manager 32-bit Rolling Decrement

cm32ri - Counter Manager 32-bit Rolling Increment

cm32rs - Counter Manager 32-bit Rolling Subtract

cm32sa - Counter Manager 32-bit Saturating Add

cm32sd - Counter Manager 32-bit Saturating Decrement

cm32si - Counter Manager 32-bit Saturating Increment

cm32ss - Counter Manager 32-bit Saturating Subtract

cm32xor - Counter Manager Xor

cm64clr - Counter Manager Clear

cm64ra - Counter Manager 64-bit Rolling Add

cm64rd - Counter Manager 64-bit Rolling Decrement

cm64ri - Counter Manager 32-bit Rolling Increment

cm64ria2 - Counter Manager 32/32 Rolling Increment/Add

cm64rs - Counter Manager 64-bit Rolling Subtract

cm64sa - Counter Manager 64-bit Saturating Add

cm64sd - Counter Manager 64-bit Saturating Decrement

cm64si - Counter Manager 64-bit Saturating Increment

cm64sia2 - Counter Manager 32/32 Saturating Increment/Add

cm64ss - Counter Manager 64-bit Saturating Subtract

cmphdr - Get a Complete Header

cnt1s - Count ones

crc32 - CRC, 32 bit input

crc32b - CRC, 8 bit input

ctc - copy to coprocessor control register

ctc0 - control to coprocessor 0

ctc1 - control to coprocessor 1

ctc2 - control to coprocessor 2

ctc3 - control to coprocessor 3

dba - Allocate a Data Buffer Pointer

dbd - Deallocate a Data Buffer Pointer

dpwt - DSTN_PORT Write

dwrd - Double Word Read

dwrdl - Double Word Read and Lock

free - Mark Header Buffer Free

j - jump

jal - jump and link

jalq10 - jump and link

jalq10-2 - jump and link, implied r31

jalr - jump and link register

jcr - jump context register

jq10 - jump

jr - jump register

lb - load byte

lbu - load byte unsigned

ldw - load double word

lh - load half word

lhu - load half word unsigned

lock - lock memory

luc32 - lookup chain 32 bits

luc32l - lookup chain 32 bits and lock

luc64 - lookup chain 64 bits

luc64l - lookup chain 64 bits and lock

lui - load upper immediate

luk - lookup key

lulck - lookup lock

lum32 - lookup match 32 bits

lum32l - lookup match 32 bits and lock

lum64 - lookup match 64 bits

lum64l - lookup match 64 bits and lock

lur - lookup read

lurl - lookup read and lock

luulck - lookup unlock

lw - load word

mcid - Allocate a Multicast ID

mfc0 - move from coprocessor 0

mfc1 - move from coprocessor 1

mfc2 - move from coprocessor 2

mfc3 - move from coprocessor 3

mrgb - merge bytes

mrgb2 - merge bytes

mrgbq10 - merge bytes

mrgbq102 - merge bytes

mtc0 - move to coprocessor 0

mtc1 - move to coprocessor 1

mtc2 - move to coprocessor 2

mtc3 - move to coprocessor 3

nor - nor

nor2 - nor

or - or

or2 - or

ori - or immediate

ori2 - or immediate

orui - or upper immediate

orui-q10 - or upper immediate

orui2 - or upper immediate

orui2-q10 - or upper immediate

pkrl - pkrl

pkrla - Packet Release Absolute

pkrlac - Packet Release Absolute Continue

pkrlah - Packet Release Absolute and Hold

pkrlau - Packet Release Absolute Unconditional

pkrli - Packet Release Immediate

pkrlic - Packet Release Immediate Continue

pkrlih - Packet Release Immediate and Hold

pkrliu - Packet Release Immediate Unconditional

pkrlr1 - pkrlr1

pkrlr30 - pkrlr30

ram - rotate and mask

rb - dma read bytes

rba - Read Bytes Absolute

rbal - Read Bytes Absolute and Lock

rbar - Read Bytes Absolute and Release

rbi - Read Bytes Immediate

rbil - Read Bytes Immediate and Lock

rbir - Read Bytes Immediate and Release

rbr1 - dma read bytes using r1

rbr30 - dma read bytes using r30

rfe - restore from exception

rx - dma read word64s

rxr1 - dma read word64s using r1

rxr30 - dma read word 64s using r30

sb - store byte

sdw - store double word

sh - store half word

sleep - sleep

sll - shift left logical

sllv - shift left logical variable

sllv2 - shift left logical variable

slmv - shift left and mask variable

slmv2 - shift left and mask variable

slt - set if less than

slt2 - set if less than

slti - set if less than immediate

slti2 - set if less than immediate

sltiu - set if less than immediate unsigned

sltiu2 - set if less than immediate unsigned

sltu - set if less than unsigned

sltu2 - set if less than unsigned

sra - shift right arithmetic

sra2 - shift right arithmetic

srav - shift right arithmetic variable

srav2 - shift right arithmetic variable

srl - shift right logical

srlv - shift right logical variable

srlv2 - shift right logical variable

srmv - shift right and mask variable

srmv2 - shift right and mask variable

srrd - sram read

srrdl - sram read and lock

srulck - sram unlock

srwr - sram write

srwru - sram write and unlock

sub - subtract

sub2 - subtract

subu - subtract unsigned

subu2 - subtract unsigned

sw - store word

swrd - Single Word Read

swrdl - Single Word Read and Lock

swwr - Single Word Write

swwru - Single Word Write and Unlock

syscall - system call

trapqfl - yield if dma queue full

trapqne - yield if dma queue not empty

traprel - traprel

tstod - Test Header Buffer Order Dependency

unlk - unlock memory

wb - dma write bytes

wba - Write Bytes Absolute

wbac - Write Bytes Absolute Cacheable

wbau - Write Bytes Absolute and Unlock

wbi - Write Bytes Immediate

wbic - Write Bytes Immediate Cacheable

wbiu - Write Bytes Immediate

wbr1 - dma write bytes using r1

wbr1u - dma write bytes using r1 and unlock

wbr30 - dma write bytes using r30

wbr30u - dma write bytes using r30 and unlock

wbu - dma write bytes and unlock

wx - dma write word64s

wxr1 - dma write word64s using r1

wxr1u - dma write word64s using r1 and unlock

wxr30 - dma write word64s using r30

wxr30u - dma write word64s using r30 and unlock

wxu - dma write word64s and unlock

xor - exclusive or

xor2 - exclusive or

xori - exclusive or immediate

xori2 - exclusive or immediate

yield - unconditional yield to the other context


Macro Instructions

Macro instructions for each machine:

iq2000 - IQ2000 packet processing engine

iq10 - IQ10 coprocessor

Individual macro-instructions descriptions


lb-base-0 - load byte - implied base 0

lbu-base-0 - load byte unsigned - implied base 0

ldw-base-0 - load double word - implied base 0

lh-base-0 - load half - implied base 0

li - load immediate

lw-base-0 - load word - implied base 0

m-add - add immediate

m-addu - add immediate unsigned

m-and - and immediate

m-avail - Mark Header Buffer Available

m-cam144 - CAM Access in 144-bit Mode

m-cam288 - CAM Access in 288-bit Mode

m-cam36 - CAM Access in 36-bit Mode

m-cam72 - CAM Access in 72-bit Mode

m-cm128ria2 - Counter Manager 128-bit 64/64 Rolling Increment/Add

m-cm128ria3 - Counter Manager 128-bit 32/32/64 Rolling Increment/Add

m-cm128ria4 - Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add

m-cm128sia2 - Counter Manager 128-bit 64/64 Saturating Inc/Add

m-cm128sia3 - Counter Manager 128-bit 32/32/64 Saturating Inc/Add

m-cm128sia4 - Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add

m-cm32and - Counter Manager And

m-cm32andn - Counter Manager And With Inverse

m-cm32mlog - Counter Manager 32-bit or R0

m-cm32or - Counter Manager Or

m-cm32ra - Counter Manager 32-bit Rolling Add

m-cm32rd - Counter Manager 32-bit Rolling Decrement

m-cm32read - Counter Manager 32-bit Rolling Add R0

m-cm32ri - Counter Manager 32-bit Rolling Increment

m-cm32rs - Counter Manager 32-bit Rolling Subtract

m-cm32sa - Counter Manager 32-bit Saturating Add

m-cm32sd - Counter Manager 32-bit Saturating Decrement

m-cm32si - Counter Manager 32-bit Saturating Increment

m-cm32ss - Counter Manager 32-bit Saturating Subtract

m-cm32xor - Counter Manager Xor

m-cm64clr - Counter Manager Clear

m-cm64ra - Counter Manager 64-bit Rolling Add

m-cm64rd - Counter Manager 64-bit Rolling Decrement

m-cm64read - Counter Manager 64-bit Rolling Add R0

m-cm64ri - Counter Manager 32-bit Rolling Increment

m-cm64ria2 - Counter Manager 32/32 Rolling Increment/Add

m-cm64rs - Counter Manager 64-bit Rolling Subtract

m-cm64sa - Counter Manager 64-bit Saturating Add

m-cm64sd - Counter Manager 64-bit Saturating Decrement

m-cm64si - Counter Manager 64-bit Saturating Increment

m-cm64sia2 - Counter Manager 32/32 Saturating Increment/Add

m-cm64ss - Counter Manager 64-bit Saturating Subtract

m-cmphdr - Get a Complete Header

m-dbd - Deallocate a Data Buffer Pointer

m-dpwt - DSTN_PORT Write

m-free -

m-j - jump register

m-lock - lock memory

m-or - or immediate

m-pkrla - Packet Release Absolute

m-pkrlac - Packet Release Absolute Continue

m-pkrlah - Packet Release Absolute and Hold

m-pkrlau - Packet Release Absolute Unconditional

m-pkrli - Packet Release Immediate

m-pkrlic - Packet Release Immediate Continue

m-pkrlih - Packet Release Immediate and Hold

m-pkrliu - Packet Release Immediate Unconditional

m-rba - Read Bytes Absolute

m-rbal - Read Bytes Absolute and Lock

m-rbar - Read Bytes Absolute and Release

m-rbi - Read Bytes Immediate

m-rbil - Read Bytes Immediate and Lock

m-rbir - Read Bytes Immediate and Release

m-sll - shift left logical

m-slt - slt immediate

m-sltu - sltu immediate

m-sra - shift right arithmetic

m-srl - shift right logical

m-sub - subtract immediate

m-subu - subtract unsigned

m-swwr - Single Word Write

m-swwru - Single Word Write and Unlock

m-tstod - Test Header Buffer Order Dependency

m-unlk -

m-wba - Write Bytes Absolute

m-wbac - Write Bytes Absolute Cacheable

m-wbau - Write Bytes Absolute and Unlock

m-wbi - Write Bytes Immediate

m-wbic - Write Bytes Immediate Cacheable

m-wbiu - Write Bytes Immediate

m-xor - xor immediate

m2-dbd - Deallocate a Data Buffer Pointer

move - move

nop - nop

not - not

sb-base-0 - store byte - implied base 0

sdw-base-0 - store double word - implied base 0

sh-base-0 - store half - implied base 0

subi - sub immediate

sw-base-0 - store word - implied base 0


This documentation was machine generated from the cgen cpu description files for this architecture.
https://sourceware.org/cgen/