31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x2d | r0 | r1 | r2 | 0x0 |
(set r2 (add SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xd | r0 | r1 | gotofflo16 |
(set r1 (add SI r0 (ext SI (trunc HI gotofflo16))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xd | r0 | r1 | imm |
(set r1 (add SI r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x28 | r0 | r1 | r2 | 0x0 |
(set r2 (and SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x18 | r0 | r1 | hi16 |
(set r1 (and SI r0 (sll SI hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x8 | r0 | r1 | uimm |
(set r1 (and SI r0 (zext SI uimm)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x30 | r0 | 0x0 | 0x0 | 0x0 |
(set pc (c-call USI "@cpu@_b_insn" r0 f-r0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-branch |
0x11 | r0 | r1 | branch |
(if (eq r0 r1) (set pc branch))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-branch |
0x12 | r0 | r1 | branch |
(if (gt r0 r1) (set pc branch))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-branch |
0x13 | r0 | r1 | branch |
(if (ge r0 r1) (set pc branch))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-branch |
0x14 | r0 | r1 | branch |
(if (geu r0 r1) (set pc branch))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-branch |
0x15 | r0 | r1 | branch |
(if (gtu r0 r1) (set pc branch))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-call |
0x38 | call |
(set pc (ext SI call))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-branch |
0x17 | r0 | r1 | branch |
(if (ne r0 r1) (set pc branch))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-exception |
0x2b | 0x2 |
(set pc (c-call USI "@cpu@_break_insn" pc))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x30 | 0x1f | 0x0 | 0x0 | 0x0 |
(set pc (c-call USI "@cpu@_bret_insn" r0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x36 | r0 | 0x0 | 0x0 | 0x0 |
(sequence () (set (reg SI h-gr 29) (add USI pc 4)) (set pc r0))
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-call |
0x3e | call |
(sequence () (set (reg SI h-gr 29) (add USI pc 4)) (set pc (ext SI call)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x39 | r0 | r1 | r2 | 0x0 |
(set r2 (eq r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x19 | r0 | r1 | imm |
(set r1 (eq r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x3a | r0 | r1 | r2 | 0x0 |
(set r2 (gt r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x3b | r0 | r1 | r2 | 0x0 |
(set r2 (ge r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x1b | r0 | r1 | imm |
(set r1 (ge r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x3c | r0 | r1 | r2 | 0x0 |
(set r2 (geu r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x1c | r0 | r1 | uimm |
(set r1 (geu r0 (zext SI uimm)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x1a | r0 | r1 | imm |
(set r1 (gt r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x3d | r0 | r1 | r2 | 0x0 |
(set r2 (gtu r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x1d | r0 | r1 | uimm |
(set r1 (gtu r0 (zext SI uimm)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x3f | r0 | r1 | r2 | 0x0 |
(set r2 (ne r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x1f | r0 | r1 | imm |
(set r1 (ne r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x23 | r0 | r1 | r2 | 0x0 |
(set pc (c-call USI "@cpu@_divu_insn" pc f-r0 f-r1 f-r2))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x30 | 0x1e | 0x0 | 0x0 | 0x0 |
(set pc (c-call USI "@cpu@_eret_insn" r0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x4 | r0 | r1 | imm |
(set r1 (ext SI (mem QI (add SI r0 (ext SI (trunc HI imm))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x4 | r0 | r1 | gotofflo16 |
(set r1 (ext SI (mem QI (add SI r0 (ext SI (trunc HI gotofflo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x4 | 0x1a | r1 | gp16 |
(set r1 (ext SI (mem QI (add SI r0 (ext SI (trunc HI gp16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x10 | r0 | r1 | imm |
(set r1 (zext SI (mem QI (add SI r0 (ext SI (trunc HI imm))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x10 | r0 | r1 | gotofflo16 |
(set r1 (zext SI (mem QI (add SI r0 (ext SI (trunc HI gotofflo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x10 | 0x1a | r1 | gp16 |
(set r1 (zext SI (mem QI (add SI r0 (ext SI (trunc HI gp16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x7 | r0 | r1 | imm |
(set r1 (ext SI (mem HI (add SI r0 (ext SI (trunc HI imm))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x7 | r0 | r1 | gotofflo16 |
(set r1 (ext SI (mem HI (add SI r0 (ext SI (trunc HI gotofflo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x7 | 0x1a | r1 | gp16 |
(set r1 (ext SI (mem HI (add SI r0 (ext SI (trunc HI gp16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xb | r0 | r1 | imm |
(set r1 (zext SI (mem HI (add SI r0 (ext SI (trunc HI imm))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xb | r0 | r1 | gotofflo16 |
(set r1 (zext SI (mem HI (add SI r0 (ext SI (trunc HI gotofflo16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xb | 0x1a | r1 | gp16 |
(set r1 (zext SI (mem HI (add SI r0 (ext SI (trunc HI gp16))))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xa | r0 | r1 | imm |
(set r1 (mem SI (add SI r0 (ext SI (trunc HI imm)))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xa | r0 | r1 | gotofflo16 |
(set r1 (mem SI (add SI r0 (ext SI (trunc HI gotofflo16)))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xa | 0x1a | r1 | got16 |
(set r1 (mem SI (add SI r0 (ext SI (trunc HI got16)))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xa | 0x1a | r1 | gp16 |
(set r1 (mem SI (add SI r0 (ext SI (trunc HI gp16)))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x31 | r0 | r1 | r2 | 0x0 |
(set pc (c-call USI "@cpu@_modu_insn" pc f-r0 f-r1 f-r2))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x22 | r0 | r1 | r2 | 0x0 |
(set r2 (mul SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x2 | r0 | r1 | imm |
(set r1 (mul SI r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x2e | r0 | 0x0 | r2 | 0x0 |
(set r2 r0)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xd | 0x1a | r1 | gp16 |
(set r1 (add SI r0 (ext SI (trunc HI gp16))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x1e | 0x0 | r1 | hi16 |
(set r1 (or SI r0 (sll SI hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xd | 0x0 | r1 | imm |
(set r1 (add SI r0 (ext SI (trunc HI imm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0xe | 0x0 | r1 | lo16 |
(set r1 (zext SI lo16))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xd | 0x0 | 0x0 | 0x0 |
(set r0 r0)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x21 | r0 | r1 | r2 | 0x0 |
(set r2 (inv SI (or SI r0 r1)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x1 | r0 | r1 | uimm |
(set r1 (inv SI (or SI r0 (zext SI uimm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x29 | r0 | 0x0 | r2 | 0x0 |
(set r2 (inv SI r0))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x2e | r0 | r1 | r2 | 0x0 |
(set r2 (or SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x1e | r0 | r1 | gotoffhi16 |
(set r1 (or SI r0 (sll SI gotoffhi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x1e | r0 | r1 | hi16 |
(set r1 (or SI r0 (sll SI hi16 16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0xe | r0 | r1 | lo16 |
(set r1 (or SI r0 (zext SI lo16)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-csr | f-r1 | f-r2 | f-resv0 |
0x24 | csr | 0x0 | r2 | 0x0 |
(set r2 csr)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x30 | 0x1d | 0x0 | 0x0 | 0x0 |
(set pc r0)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xc | r0 | r1 | imm |
(set (mem QI (add SI r0 (ext SI (trunc HI imm)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xc | r0 | r1 | gotofflo16 |
(set (mem QI (add SI r0 (ext SI (trunc HI gotofflo16)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xc | 0x1a | r1 | gp16 |
(set (mem QI (add SI r0 (ext SI (trunc HI gp16)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-exception |
0x2b | 0x7 |
(set pc (c-call USI "@cpu@_scall_insn" pc))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x2c | r0 | 0x0 | r2 | 0x0 |
(set r2 (ext SI (trunc QI r0)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x37 | r0 | 0x0 | r2 | 0x0 |
(set r2 (ext SI (trunc HI r0)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x3 | r0 | r1 | imm |
(set (mem HI (add SI r0 (ext SI (trunc HI imm)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x3 | r0 | r1 | gotofflo16 |
(set (mem HI (add SI r0 (ext SI (trunc HI gotofflo16)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x3 | 0x1a | r1 | gp16 |
(set (mem HI (add SI r0 (ext SI (trunc HI gp16)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x2f | r0 | r1 | r2 | 0x0 |
(set r2 (sll SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0xf | r0 | r1 | imm |
(set r1 (sll SI r0 imm))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x25 | r0 | r1 | r2 | 0x0 |
(set r2 (sra SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x5 | r0 | r1 | imm |
(set r1 (sra SI r0 imm))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x20 | r0 | r1 | r2 | 0x0 |
(set r2 (srl SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x0 | r0 | r1 | imm |
(set r1 (srl SI r0 imm))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x32 | r0 | r1 | r2 | 0x0 |
(set r2 (sub SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x16 | r0 | r1 | imm |
(set (mem SI (add SI r0 (ext SI (trunc HI imm)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x16 | r0 | r1 | gotofflo16 |
(set (mem SI (add SI r0 (ext SI (trunc HI gotofflo16)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-imm |
0x16 | 0x1a | r1 | gp16 |
(set (mem SI (add SI r0 (ext SI (trunc HI gp16)))) r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-user |
0x33 | r0 | r1 | r2 | user |
(set r2 (c-call SI "@cpu@_user_insn" r0 r1 user))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-csr | f-r1 | f-r2 | f-resv0 |
0x34 | csr | r1 | 0x0 | 0x0 |
(c-call VOID "@cpu@_wcsr_insn" f-csr r1)
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x29 | r0 | r1 | r2 | 0x0 |
(set r2 (inv SI (xor SI r0 r1)))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x9 | r0 | r1 | uimm |
(set r1 (inv SI (xor SI r0 (zext SI uimm))))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 | 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-r2 | f-resv0 |
0x26 | r0 | r1 | r2 | 0x0 |
(set r2 (xor SI r0 r1))
31 30 29 28 27 26 | 25 24 23 22 21 | 20 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-opcode | f-r0 | f-r1 | f-uimm |
0x6 | r0 | r1 | uimm |
(set r1 (xor SI r0 (zext SI uimm)))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/