15 14 13 12 | 11 10 9 | 8 | 7 6 5 4 3 | 2 1 0 |
f-15-4 | f-rx | f-8-1 | f-opmode | f-ry |
0xc | rx | 0x1 | 0x9 | ry |
(sequence ((SI temp)) (set temp (reg SI h-ar rx)) (set (reg SI h-ar rx) (reg SI h-ar ry)) (set (reg SI h-ar ry) temp))
15 14 13 12 | 11 10 9 | 8 | 7 6 5 4 3 | 2 1 0 |
f-15-4 | f-rx | f-8-1 | f-opmode | f-ry |
0xc | rx | 0x1 | 0x8 | ry |
(sequence ((SI temp)) (set temp (reg SI h-dr rx)) (set (reg SI h-dr rx) (reg SI h-dr ry)) (set (reg SI h-dr ry) temp))
15 14 13 12 | 11 10 9 | 8 | 7 6 5 4 3 | 2 1 0 |
f-15-4 | f-rx | f-8-1 | f-opmode | f-ry |
0xc | rx | 0x1 | 0x11 | ry |
(sequence ((SI temp)) (set temp (reg SI h-dr rx)) (set (reg SI h-dr rx) (reg SI h-ar ry)) (set (reg SI h-ar ry) temp))
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4afc |
(nop)
15 14 13 12 | 11 10 9 | 8 | 7 6 5 4 3 2 1 0 |
f-15-4 | f-rx | f-8-1 | f-imm8 |
0x7 | reg-@2 | 0x0 | imm8 |
(sequence () (set (reg SI h-dr reg-@2) (ext SI imm8)))
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4e71 |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4e70 |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4e73 |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4e77 |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4e75 |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 | 3 2 1 0 |
f-15-12 | f-vector |
0x4e4 | vector |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-15-16 |
0x4e76 |
(nop)
15 14 13 12 11 10 9 8 7 6 5 4 3 | 2 1 0 |
f-15-13 | f-rx |
0x9cb | reg-@2 |
(nop)
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/