31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x0 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (add SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x0 | 0x1 | frsr1 | frdr | imm16 |
(sequence ((HI tmp)) (set tmp (and INT imm16 65535)) (set frdr (add SI frsr1 (ext SI tmp))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x1 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (add USI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0x1 | 0x1 | frsr1 | frdr | imm16z |
(set frdr (add USI frsr1 (ext USI imm16z)))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x8 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (and SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0x8 | 0x1 | frsr1 | frdr | imm16z |
(set frdr (and SI frsr1 (ext USI imm16z)))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x12 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (sra SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x12 | 0x1 | frsr1 | frdr | imm16 |
(set frdr (sra SI frsr1 imm16))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu24 |
0x0 | 0x34 | 0x0 | 0x0 |
(c-call VOID "do_break" pc)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-imm16s |
0x0 | 0x1a | 0x1 | frsr1 | frsr2 | imm16o |
(sequence () (if (eq frsr1 frsr2) (set (delay USI 1 pc) (add USI pc (ext SI imm16o)))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-imm16s |
0x0 | 0x19 | 0x1 | frsr1 | frsr2 | imm16o |
(sequence () (if (le frsr1 frsr2) (set (delay USI 1 pc) (add USI pc (ext SI imm16o)))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-imm16s |
0x0 | 0x18 | 0x1 | frsr1 | frsr2 | imm16o |
(sequence () (if (lt frsr1 frsr2) (set (delay USI 1 pc) (add USI pc (ext SI imm16o)))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-imm16s |
0x0 | 0x1d | 0x1 | frsr1 | frsr2 | imm16o |
(sequence () (if (not BI (eq frsr1 frsr2)) (set (delay USI 1 pc) (add USI pc (ext SI imm16o)))))
31 | 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-mask | f-uu-3-9 | f-rc2 | f-ctxdisp |
0x1 | 0x10 | mask | 0x0 | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-uu4a | f-imm16s |
0x0 | 0x1e | 0x1 | frsr1 | 0x0 | imm16o |
(sequence () (if (not BI (eq frsr1 0)) (set (delay USI 1 pc) (add USI pc (ext SI imm16o)))))
31 | 30 29 28 27 26 | 25 24 23 | 22 21 20 | 19 18 17 16 15 14 | 13 12 11 10 9 8 | 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-cb1sel | f-cb2sel | f-cb1incr | f-cb2incr | f-rc3 | f-rc2 | f-ctxdisp |
0x1 | 0x0 | cb1sel | cb2sel | cb1incr | cb2incr | rc3 | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 23 | 22 21 20 | 19 18 17 16 | 15 14 13 | 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-cb1sel | f-cb2sel | f-sr2 | f-length | f-rownum1 | f-rownum2 | f-rc2 | f-ctxdisp |
0x1 | 0x3 | cb1sel | cb2sel | frsr2 | length | rownum1 | rownum2 | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu4b | f-uu4a | f-uu16 |
0x0 | 0x31 | 0x0 | 0x0 | 0x0 | 0x0 |
(c-call VOID "disable_interrupts")
31 | 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-mask | f-cell | f-rc2 | f-ctxdisp |
0x1 | 0x11 | mask | cell | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 23 | 22 21 20 | 19 18 17 16 15 14 | 13 12 11 10 9 8 | 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-cb1sel | f-cb2sel | f-cb1incr | f-cb2incr | f-uu1 | f-rc2 | f-ctxdisp |
0x1 | 0x1 | cb1sel | cb2sel | cb1incr | cb2incr | 0x0 | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu4b | f-uu4a | f-uu16 |
0x0 | 0x30 | 0x0 | 0x0 | 0x0 | 0x0 |
(c-call VOID "enable_interrupts")
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-ball | f-brc | f-uu-4-15 | f-rc | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0x3 | rbbc | frsr1 | ball | brc | 0x0 | rc | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 | 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-sr2 | f-ball2 | f-brc2 | f-rc1 | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0xd | rbbc | frsr1 | frsr2 | ball2 | brc2 | rc1 | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 15 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-incamt | f-rc1 | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0x15 | rbbc | frsr1 | incamt | rc1 | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 | 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-perm | f-sr1 | f-ball | f-colnum | f-uu-1-15 | f-cbx | f-ccb | f-cdb | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x1e | perm | frsr1 | ball | colnum | 0x0 | cbx | ccb | cdb | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 | 22 21 20 | 19 18 | 17 16 15 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-perm | f-a23 | f-cr | f-cbs | f-incr | f-ccb | f-cdb | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x1c | perm | a23 | cr | cbs | incr | ccb | cdb | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-ball | f-brc | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0x5 | rbbc | frsr1 | ball | brc | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-ball | f-brc | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0x7 | rbbc | frsr1 | ball | brc | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-ball | f-brc | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0x6 | rbbc | frsr1 | ball | brc | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-ball | f-brc | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0x8 | rbbc | frsr1 | ball | brc | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 23 | 22 21 20 | 19 18 17 16 15 14 | 13 12 11 10 9 8 | 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-cb1sel | f-cb2sel | f-cb1incr | f-cb2incr | f-rc3 | f-rc2 | f-ctxdisp |
0x1 | 0x2 | cb1sel | cb2sel | cb1incr | cb2incr | rc3 | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu24 |
0x0 | 0x35 | 0x0 | 0x0 |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 | 14 | 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-msopc | f-mode | f-sr1 | f-sr2 | f-uu-1-15 | f-id | f-size |
0x1 | 0x17 | mode | frsr1 | frsr2 | 0x0 | id | size |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-uu4a | f-drrr | f-uu12 |
0x0 | 0x1c | 0x0 | frsr1 | 0x0 | frdrrr | 0x0 |
(sequence () (if (eq frsr1 0) (c-call VOID "do_syscall" pc) (sequence () (set (delay SI 1 frdrrr) (add USI pc 8)) (set (delay USI 1 pc) frsr1))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu4b | f-uu4a | f-imm16s |
0x0 | 0x1b | 0x1 | 0x0 | 0x0 | imm16o |
(set (delay USI 1 pc) (add USI pc (ext SI imm16o)))
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 | 14 13 12 | 11 10 9 | 8 7 6 5 4 3 2 1 0 |
f-msys | f-msopc | f-uu-2-25 | f-sr1 | f-sr2 | f-rc | f-rcnum | f-uu-3-11 | f-contnum |
0x1 | 0x0 | 0x0 | frsr1 | frsr2 | rc | rcnum | 0x0 | contnum |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-msopc | f-uu-2-25 | f-sr1 | f-sr2 | f-imm16u |
0x1 | 0x1 | 0x0 | frsr1 | frsr2 | imm16z |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu4b | f-dr | f-imm16u |
0x0 | 0xe | 0x1 | 0x0 | frdr | imm16z |
(set frdr (and UINT (sll UINT imm16z 16) 4294901760))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x20 | 0x1 | frsr1 | frdr | imm16 |
(sequence ((USI ea) (HI tmp)) (set tmp (and INT imm16 65535)) (set ea (and SI (add SI frsr1 (ext SI tmp)) 4294967292)) (set frdr (mem SI ea)))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-uu4a | f-uu8 | f-loopo |
0x0 | 0x1f | 0x0 | frsr1 | 0x0 | 0x0 | loopsize |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-imm16l | f-loopo |
0x0 | 0x1f | 0x1 | imm16l | loopsize |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x10 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (sll SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x10 | 0x1 | frsr1 | frdr | imm16 |
(set frdr (sll SI frsr1 imm16))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x11 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (srl SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x11 | 0x1 | frsr1 | frdr | imm16 |
(set frdr (srl SI frsr1 imm16))
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-sr2 | f-uu-4-15 | f-rc1 | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0x4 | rbbc | frsr1 | frsr2 | 0x0 | rc1 | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 | 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-perm | f-sr1 | f-sr2 | f-uu-1-15 | f-cbx | f-ccb | f-cdb | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x1f | perm | frsr1 | frsr2 | 0x0 | cbx | ccb | cdb | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 | 17 16 15 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-perm | f-sr1 | f-cbs | f-incr | f-ccb | f-cdb | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x1d | perm | frsr1 | cbs | incr | ccb | cdb | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-sr2 | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0x9 | rbbc | frsr1 | frsr2 | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-sr2 | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0xb | rbbc | frsr1 | frsr2 | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-sr2 | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0xa | rbbc | frsr1 | frsr2 | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-sr2 | f-fbdisp | f-cell | f-dup | f-ctxdisp |
0x1 | 0xc | rbbc | frsr1 | frsr2 | fbdisp | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 | 21 20 | 19 18 17 16 | 15 | 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-uu-2-23 | f-type | f-sr2 | f-uu-1-15 | f-rownum | f-rc1 | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0xf | rbbc | 0x0 | type | frsr2 | 0x0 | rownum | rc1 | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x4 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(sequence ((HI op1) (HI op2)) (set op1 (and SI frsr1 65535)) (if (or BI (lt op1 -32768) (gt op1 32767)) (error VOID "operand out of range")) (set op2 (and SI frsr2 65535)) (if (or BI (lt op2 -32768) (gt op2 32767)) (error VOID "operand out of range")) (set frdrrr (mul SI (ext SI op1) (ext SI op2))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x4 | 0x1 | frsr1 | frdr | imm16 |
(sequence ((HI op1) (HI op2)) (set op1 (and SI frsr1 65535)) (if (or BI (lt op1 -32768) (gt op1 32767)) (error VOID "operand out of range")) (set op2 (and INT imm16 65535)) (if (eq op1 0) (error VOID "op1 is 0")) (if (eq op2 0) (error VOID "op2 is 0")) (set frdr (mul SI (ext SI op1) (ext SI op2))))
31 | 30 29 28 27 26 | 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 | 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rda | f-wr | f-fbincr | f-sr2 | f-length | f-rownum1 | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x19 | rda | wr | fbincr | frsr2 | length | rownum1 | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 | 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rda | f-wr | f-sr1 | f-sr2 | f-length | f-rownum1 | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x1b | rda | wr | frsr1 | frsr2 | length | rownum1 | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0xb | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (inv SI (and SI frsr1 frsr2)))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0xb | 0x1 | frsr1 | frdr | imm16z |
(set frdr (inv SI (and SI frsr1 (ext USI imm16z))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu24 |
0x0 | 0x9 | 0x0 | 0x0 |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0xc | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (inv SI (or SI frsr1 frsr2)))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0xc | 0x1 | frsr1 | frdr | imm16z |
(set frdr (inv SI (or SI frsr1 (ext USI imm16z))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x9 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (or SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0x9 | 0x1 | frsr1 | frdr | imm16z |
(set frdr (or SI frsr1 (ext USI imm16z)))
31 | 30 29 28 27 26 | 25 24 | 23 22 | 21 20 | 19 | 18 17 16 | 15 | 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-uu-2-23 | f-type | f-ball | f-brc | f-uu-1-15 | f-rownum | f-rc1 | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0xe | rbbc | 0x0 | type | ball | brc | 0x0 | rownum | rc1 | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 12 | 11 | 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rbbc | f-sr1 | f-uu-1-19 | f-colnum | f-drrr | f-rc1 | f-cbrb | f-cell | f-dup | f-ctxdisp |
0x1 | 0x14 | rbbc | frsr1 | 0x0 | colnum | frdrrr | rc1 | cbrb | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 | 24 | 23 | 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rda | f-wr | f-xmode | f-mask1 | f-sr2 | f-fbdisp | f-rownum2 | f-rc2 | f-ctxdisp |
0x1 | 0x16 | rda | wr | xmode | mask1 | frsr2 | fbdisp | rownum2 | rc2 | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-uu4a | f-uu16 |
0x0 | 0x33 | 0x0 | frsr1 | 0x0 | 0x0 |
(sequence () (c-call VOID "enable_interrupts") (set (delay USI 1 pc) frsr1))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-uu4b | f-uu4a | f-drrr | f-uu12 |
0x0 | 0x32 | 0x0 | 0x0 | 0x0 | frdrrr | 0x0 |
(sequence () (set frdrrr (add USI pc 4)) (c-call VOID "do_syscall" pc))
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-msopc | f-uu-2-25 | f-sr1 | f-sr2 | f-imm16u |
0x1 | 0x2 | 0x0 | frsr1 | frsr2 | imm16z |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-imm16s |
0x0 | 0x21 | 0x1 | frsr1 | frsr2 | imm16 |
(sequence ((USI ea) (HI tmp)) (set tmp (and INT imm16 65535)) (set ea (and SI (add SI frsr1 (ext SI tmp)) 4294967292)) (set (mem SI ea) frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x2 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (sub SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16s |
0x0 | 0x2 | 0x1 | frsr1 | frdr | imm16 |
(sequence ((HI tmp)) (set tmp (and INT imm16 65535)) (set frdr (sub SI frsr1 (ext SI tmp))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0x3 | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (sub USI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0x3 | 0x1 | frsr1 | frdr | imm16z |
(set frdr (sub USI frsr1 (ext USI imm16z)))
31 | 30 29 28 27 26 | 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-uu-2-25 | f-sr1 | f-sr2 | f-fbdisp | f-rownum2 | f-uu-1-6 | f-ctxdisp |
0x1 | 0x13 | 0x0 | frsr1 | frsr2 | fbdisp | rownum2 | 0x0 | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 24 23 22 21 20 19 18 17 16 15 14 13 | 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-bankaddr | f-rownum1 | f-cell | f-dup | f-ctxdisp |
0x1 | 0x12 | bankaddr | rownum1 | cell | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 | 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 | 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rda | f-wr | f-fbincr | f-ball | f-colnum | f-length | f-rownum1 | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x18 | rda | wr | fbincr | ball | colnum | length | rownum1 | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 | 25 | 24 | 23 22 21 20 | 19 | 18 17 16 | 15 14 13 | 12 11 10 | 9 8 7 | 6 | 5 4 3 2 1 0 |
f-msys | f-msopc | f-rda | f-wr | f-sr1 | f-ball | f-colnum | f-length | f-rownum1 | f-rownum2 | f-dup | f-ctxdisp |
0x1 | 0x1a | rda | wr | frsr1 | ball | colnum | length | rownum1 | rownum2 | dup | ctxdisp |
(nop)
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0xd | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (inv SI (xor SI frsr1 frsr2)))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0xd | 0x1 | frsr1 | frdr | imm16z |
(set frdr (inv SI (xor SI frsr1 (ext USI imm16z))))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-sr2 | f-drrr | f-uu12 |
0x0 | 0xa | 0x0 | frsr1 | frsr2 | frdrrr | 0x0 |
(set frdrrr (xor SI frsr1 frsr2))
31 | 30 29 28 27 26 25 | 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
f-msys | f-opc | f-imm | f-sr1 | f-dr | f-imm16u |
0x0 | 0xa | 0x1 | frsr1 | frdr | imm16z |
(set frdr (xor SI frsr1 (ext USI imm16z)))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/