OR1K Instruction Documentation

Instructions

Instructions for each machine:

or32 - Generic OpenRISC 1000 32-bit CPU

MEM - Memory
ALU - ALU
FPU - FPU
BR - Branch
alphabetically

or32nd - Generic OpenRISC 1000 32-bit CPU with no branch delay slot

MEM - Memory
ALU - ALU
FPU - FPU
BR - Branch
alphabetically

or64 - Generic OpenRISC 1000 64-bit CPU

MEM - Memory
ALU - ALU
FPU - FPU
BR - Branch
alphabetically

or64nd - Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot

MEM - Memory
ALU - ALU
FPU - FPU
BR - Branch
alphabetically

Individual instructions descriptions

l-add - l.add reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.add $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0x0

semantics:

(sequence
  ()
  (sequence
    ()
    (set sys-sr-cy (addc-cflag WI rA rB 0))
    (set sys-sr-ov (addc-oflag WI rA rB 0))
    (set rD (add WI rA rB)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-addc - l.addc reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.addc $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0x1

semantics:

(sequence
  ()
  (sequence
    ((BI tmp-sys-sr-cy))
    (set tmp-sys-sr-cy sys-sr-cy)
    (set sys-sr-cy
         (addc-cflag WI rA rB tmp-sys-sr-cy))
    (set sys-sr-ov
         (addc-oflag WI rA rB tmp-sys-sr-cy))
    (set rD (addc WI rA rB tmp-sys-sr-cy)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-addi - l.addi reg/reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.addi $rD,$rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x27 rD rA simm16

semantics:

(sequence
  ()
  (sequence
    ()
    (set sys-sr-cy
         (addc-cflag WI rA (ext WI simm16) 0))
    (set sys-sr-ov
         (addc-oflag WI rA (ext WI simm16) 0))
    (set rD (add WI rA (ext WI simm16))))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-addic - l.addic reg/reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.addic $rD,$rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x28 rD rA simm16

semantics:

(sequence
  ()
  (sequence
    ((BI tmp-sys-sr-cy))
    (set tmp-sys-sr-cy sys-sr-cy)
    (set sys-sr-cy
         (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy))
    (set sys-sr-ov
         (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy))
    (set rD
         (addc WI rA (ext WI simm16) tmp-sys-sr-cy)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-adrp - adrp reg/disp21

machines: or32 or32nd or64 or64nd

syntax: l.adrp $rD,${disp21}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-disp21

0x2 rD disp21

semantics:

(set rD
     (add WI (sll UDI disp21 13) (and UDI pc -8192)))

l-and - l.and reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.and $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0x3

semantics:
```
(set rD (and UDI rA rB))
```

l-andi - l.and reg/reg/uimm16

machines: or32 or32nd or64 or64nd

syntax: l.andi $rD,$rA,$uimm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-uimm16

0x29 rD rA uimm16

semantics:

(set rD (and UDI rA (zext UWI uimm16)))

l-bf - branch if condition bit set (pc relative iaddr)

machines: or32 or32nd or64 or64nd

syntax: l.bf ${disp26}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-disp26

0x4 disp26

semantics:

(sequence
  ()
  (if sys-sr-f
      (delay VOID 1 (set pc disp26))
      (if sys-cpucfgr-nd
          (delay VOID 1 (set pc (add UDI pc 4)))))
  (if sys-cpucfgr-nd (skip VOID 1)))

l-bnf - branch if condition bit not set (pc relative iaddr)

machines: or32 or32nd or64 or64nd

syntax: l.bnf ${disp26}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-disp26

0x3 disp26

semantics:

(sequence
  ()
  (if (not UDI sys-sr-f)
      (delay VOID 1 (set pc disp26))
      (if sys-cpucfgr-nd
          (delay VOID 1 (set pc (add UDI pc 4)))))
  (if sys-cpucfgr-nd (skip VOID 1)))

l-cmov - l.cmov reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.cmov $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10	9 8	7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-1	f-op-9-2	f-resv-7-4	f-op-3-4
0x38	rD	rA	rB	0x0	0x0	0x0	0xe

semantics:
```
(if sys-sr-f (set rD rA) (set rD rB))
```

l-csync - context sync

machines: or32 or32nd or64 or64nd

syntax: l.csync

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-resv-20-21

0x8 0x18 0x0

semantics:
```
(nop)
```

l-cust1 - l.cust1

machines: or32 or32nd or64 or64nd

syntax: l.cust1

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x1c 0x0

semantics:
```
(nop)
```

l-cust2 - l.cust2

machines: or32 or32nd or64 or64nd

syntax: l.cust2

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x1d 0x0

semantics:
```
(nop)
```

l-cust3 - l.cust3

machines: or32 or32nd or64 or64nd

syntax: l.cust3

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x1e 0x0

semantics:
```
(nop)
```

l-cust4 - l.cust4

machines: or32 or32nd or64 or64nd

syntax: l.cust4

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x1f 0x0

semantics:
```
(nop)
```

l-cust5 - l.cust5

machines: or32 or32nd or64 or64nd

syntax: l.cust5

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x3c 0x0

semantics:
```
(nop)
```

l-cust6 - l.cust6

machines: or32 or32nd or64 or64nd

syntax: l.cust6

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x3d 0x0

semantics:
```
(nop)
```

l-cust7 - l.cust7

machines: or32 or32nd or64 or64nd

syntax: l.cust7

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x3e 0x0

semantics:
```
(nop)
```

l-cust8 - l.cust8

machines: or32 or32nd or64 or64nd

syntax: l.cust8

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x3f 0x0

semantics:
```
(nop)
```

l-div - divide (signed)

machines: or32 or32nd or64 or64nd

syntax: l.div $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x30	0x9

semantics:

(if (ne rB 0)
    (sequence
      ()
      (set sys-sr-ov 0)
      (set rD (div WI rA rB)))
    (sequence
      ()
      (set sys-sr-ov 1)
      (if sys-sr-ove
          (c-call
            VOID
            "@cpu@_exception"
            pc
            (enum INT EXCEPT-RANGE)))))

l-divu - divide (unsigned)

machines: or32 or32nd or64 or64nd

syntax: l.divu $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x30	0xa

semantics:

(if (ne rB 0)
    (sequence
      ()
      (set sys-sr-cy 0)
      (set rD (udiv UWI rA rB)))
    (sequence
      ()
      (set sys-sr-cy 1)
      (if sys-sr-ove
          (c-call
            VOID
            "@cpu@_exception"
            pc
            (enum INT EXCEPT-RANGE)))))

l-extbs - l.extbs reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.extbs $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10	9 8 7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-6	f-op-9-4	f-resv-5-2	f-op-3-4
0x38	rD	rA	0x0	0x1	0x0	0xc

semantics:
```
(set rD (ext WI (trunc QI rA)))
```

l-extbz - l.extbz reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.extbz $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10	9 8 7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-6	f-op-9-4	f-resv-5-2	f-op-3-4
0x38	rD	rA	0x0	0x3	0x0	0xc

semantics:
```
(set rD (zext UWI (trunc UQI rA)))
```

l-exths - l.exths reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.exths $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10	9 8 7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-6	f-op-9-4	f-resv-5-2	f-op-3-4
0x38	rD	rA	0x0	0x0	0x0	0xc

semantics:
```
(set rD (ext WI (trunc HI rA)))
```

l-exthz - l.exthz reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.exthz $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10	9 8 7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-6	f-op-9-4	f-resv-5-2	f-op-3-4
0x38	rD	rA	0x0	0x2	0x0	0xc

semantics:
```
(set rD (zext UWI (trunc UHI rA)))
```

l-extws - l.extws reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.extws $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10	9 8 7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-6	f-op-9-4	f-resv-5-2	f-op-3-4
0x38	rD	rA	0x0	0x0	0x0	0xd

semantics:
```
(set rD (ext WI (trunc SI rA)))
```

l-extwz - l.extwz reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.extwz $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10	9 8 7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-6	f-op-9-4	f-resv-5-2	f-op-3-4
0x38	rD	rA	0x0	0x1	0x0	0xd

semantics:
```
(set rD (zext USI (trunc USI rA)))
```

l-ff1 - find first '1'

machines: or32 or32nd or64 or64nd

syntax: l.ff1 $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0xf

semantics:
```
(set rD (c-call UWI "@cpu@_ff1" rA))
```

l-fl1 - find last '1'

machines: or32 or32nd or64 or64nd

syntax: l.fl1 $rD,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x10	0xf

semantics:
```
(set rD (c-call UWI "@cpu@_fl1" rA))
```

l-j - jump (pc-relative iaddr)

machines: or32 or32nd or64 or64nd

syntax: l.j ${disp26}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-disp26

0x0 disp26

semantics:

(sequence
  ()
  (delay VOID 1 (set pc disp26))
  (if sys-cpucfgr-nd (skip VOID 1)))

l-jal - jump and link (pc-relative iaddr)

machines: or32 or32nd or64 or64nd

syntax: l.jal ${disp26}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-disp26

0x1 disp26

semantics:

(sequence
  ()
  (set (reg UDI h-gpr 9)
       (add UDI pc (if INT sys-cpucfgr-nd 4 8)))
  (sequence
    ()
    (delay VOID 1 (set pc disp26))
    (if sys-cpucfgr-nd (skip VOID 1))))

l-jalr - jump register and link (absolute iaddr)

machines: or32 or32nd or64 or64nd

syntax: l.jalr $rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-10 f-r3 f-resv-10-11

0x12 0x0 rB 0x0

semantics:

(sequence
  ()
  (set (reg UDI h-gpr 9)
       (add UDI pc (if INT sys-cpucfgr-nd 4 8)))
  (sequence
    ()
    (delay VOID 1 (set pc rB))
    (if sys-cpucfgr-nd (skip VOID 1))))

l-jr - jump register (absolute iaddr)

machines: or32 or32nd or64 or64nd

syntax: l.jr $rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-10 f-r3 f-resv-10-11

0x11 0x0 rB 0x0

semantics:

(sequence
  ()
  (delay VOID 1 (set pc rB))
  (if sys-cpucfgr-nd (skip VOID 1)))

l-lbs - l.lbs reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lbs $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x24 rD rA simm16

semantics:

(set rD
     (ext WI
          (mem QI
               (c-call
                 AI
                 "@cpu@_make_load_store_addr"
                 rA
                 (ext SI simm16)
                 1))))

l-lbz - l.lbz reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lbz $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x23 rD rA simm16

semantics:

(set rD
     (zext UWI
           (mem UQI
                (c-call
                  AI
                  "@cpu@_make_load_store_addr"
                  rA
                  (ext SI simm16)
                  1))))

l-lhs - l.lhs reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lhs $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x26 rD rA simm16

semantics:

(set rD
     (ext WI
          (mem HI
               (c-call
                 AI
                 "@cpu@_make_load_store_addr"
                 rA
                 (ext SI simm16)
                 2))))

l-lhz - l.lhz reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lhz $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x25 rD rA simm16

semantics:

(set rD
     (zext UWI
           (mem UHI
                (c-call
                  AI
                  "@cpu@_make_load_store_addr"
                  rA
                  (ext SI simm16)
                  2))))

l-lwa - l.lwa reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lwa $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x1b rD rA simm16

semantics:

(sequence
  ()
  (set rD
       (zext UWI
             (mem USI
                  (c-call
                    AI
                    "@cpu@_make_load_store_addr"
                    rA
                    (ext SI simm16)
                    4))))
  (set atomic-reserve 1)
  (set atomic-address
       (c-call
         AI
         "@cpu@_make_load_store_addr"
         rA
         (ext SI simm16)
         4)))

l-lws - l.lws reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lws $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x22 rD rA simm16

semantics:

(set rD
     (ext WI
          (mem SI
               (c-call
                 AI
                 "@cpu@_make_load_store_addr"
                 rA
                 (ext SI simm16)
                 4))))

l-lwz - l.lwz reg/simm16(reg)

machines: or32 or32nd or64 or64nd

syntax: l.lwz $rD,${simm16}($rA)

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x21 rD rA simm16

semantics:

(set rD
     (zext UWI
           (mem USI
                (c-call
                  AI
                  "@cpu@_make_load_store_addr"
                  rA
                  (ext SI simm16)
                  4))))

l-mac - l.mac reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.mac $rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-op-25-5	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x31	0x0	rA	rB	0x0	0x1

semantics:

(sequence
  ()
  (sequence
    ((DI prod) (DI mac) (DI result))
    (set prod (mul DI (ext DI rA) (ext DI rB)))
    (set mac (join DI SI mac-machi mac-maclo))
    (set result (add DI prod mac))
    (set mac-machi (subword SI result 0))
    (set mac-maclo (subword SI result 1))
    (set sys-sr-ov (addc-oflag DI prod mac 0)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-maci - l.maci reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.maci $rA,${simm16}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-5 f-r2 f-simm16

0x13 0x0 rA simm16

semantics:

(sequence
  ()
  (sequence
    ((DI prod) (DI mac) (DI result))
    (set prod (mul DI (ext DI rA) (ext DI simm16)))
    (set mac (join DI SI mac-machi mac-maclo))
    (set result (add DI mac prod))
    (set mac-machi (subword SI result 0))
    (set mac-maclo (subword SI result 1))
    (set sys-sr-ov (addc-oflag DI prod mac 0)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-macrc - macrc reg

machines: or32 or32nd or64 or64nd

syntax: l.macrc $rD

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-resv-20-4 f-op-16-1 f-uimm16

0x6 rD 0x0 0x1 0x0

semantics:

(sequence
  ()
  (set rD mac-maclo)
  (set mac-maclo 0)
  (set mac-machi 0))

l-macu - l.macu reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.macu $rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-op-25-5	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x31	0x0	rA	rB	0x0	0x3

semantics:

(sequence
  ()
  (sequence
    ((DI prod) (DI mac) (DI result))
    (set prod (mul DI (zext DI rA) (zext DI rB)))
    (set mac (join DI SI mac-machi mac-maclo))
    (set result (add DI prod mac))
    (set mac-machi (subword SI result 0))
    (set mac-maclo (subword SI result 1))
    (set sys-sr-cy (addc-cflag DI prod mac 0)))
  (if (andif sys-sr-cy sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-mfspr - mfspr

machines: or32 or32nd or64 or64nd

syntax: l.mfspr $rD,$rA,${uimm16}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-uimm16

0x2d rD rA uimm16

semantics:

(set rD
     (c-call
       UWI
       "@cpu@_mfspr"
       (or UDI rA (zext UWI uimm16))))

l-movhi - movhi reg/uimm16

machines: or32 or32nd or64 or64nd

syntax: l.movhi $rD,$uimm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-resv-20-4 f-op-16-1 f-uimm16

0x6 rD 0x0 0x0 uimm16

semantics:

(set rD (sll UWI (zext UWI uimm16) 16))

l-msb - l.msb reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.msb $rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-op-25-5	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x31	0x0	rA	rB	0x0	0x2

semantics:

(sequence
  ()
  (sequence
    ((DI prod) (DI mac) (DI result))
    (set prod (mul DI (ext DI rA) (ext DI rB)))
    (set mac (join DI SI mac-machi mac-maclo))
    (set result (sub DI mac prod))
    (set mac-machi (subword SI result 0))
    (set mac-maclo (subword SI result 1))
    (set sys-sr-ov (subc-oflag DI mac result 0)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-msbu - l.msbu reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.msbu $rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-op-25-5	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x31	0x0	rA	rB	0x0	0x4

semantics:

(sequence
  ()
  (sequence
    ((DI prod) (DI mac) (DI result))
    (set prod (mul DI (zext DI rA) (zext DI rB)))
    (set mac (join DI SI mac-machi mac-maclo))
    (set result (sub DI mac prod))
    (set mac-machi (subword SI result 0))
    (set mac-maclo (subword SI result 1))
    (set sys-sr-cy (subc-cflag DI mac result 0)))
  (if (andif sys-sr-cy sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-msync - memory sync

machines: or32 or32nd or64 or64nd

syntax: l.msync

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-resv-20-21

0x8 0x10 0x0

semantics:
```
(nop)
```

l-mtspr - mtspr

machines: or32 or32nd or64 or64nd

syntax: l.mtspr $rA,$rB,${uimm16-split}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r2 f-r3 f-uimm16-split

0x30 rA rB uimm16-split

semantics:

(c-call
  VOID
  "@cpu@_mtspr"
  (or UDI rA (zext WI uimm16-split))
  rB)

l-mul - l.mul reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.mul $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x30	0x6

semantics:

(sequence
  ()
  (sequence
    ()
    (set sys-sr-ov (mul-o2flag WI rA rB))
    (set rD (mul WI rA rB)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-muld - l.muld reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.muld $rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-resv-25-5	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	0x0	rA	rB	0x30	0x7

semantics:

(sequence
  ((DI result))
  (set result (mul DI (ext DI rA) (ext DI rB)))
  (set mac-machi (subword SI result 0))
  (set mac-maclo (subword SI result 1)))

l-muldu - l.muld reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.muldu $rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-resv-25-5	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	0x0	rA	rB	0x30	0xd

semantics:

(sequence
  ((DI result))
  (set result (mul DI (zext DI rA) (zext DI rB)))
  (set mac-machi (subword SI result 0))
  (set mac-maclo (subword SI result 1)))

l-muli - l.muli reg/reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.muli $rD,$rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x2c rD rA simm16

semantics:

(sequence
  ()
  (sequence
    ()
    (set sys-sr-ov
         (mul-o2flag WI rA (ext WI simm16)))
    (set rD (mul WI rA (ext WI simm16))))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-mulu - l.mulu reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.mulu $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x30	0xb

semantics:

(sequence
  ()
  (sequence
    ()
    (set sys-sr-cy (mul-o1flag UWI rA rB))
    (set rD (mul UWI rA rB)))
  (if (andif sys-sr-cy sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-nop - nop

machines: or32 or32nd or64 or64nd

syntax: l.nop

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-2 f-resv-23-8 f-uimm16

0x5 0x1 0x0 uimm16

semantics:
```
(nop)
```

l-nop-imm - nop uimm16

machines: or32 or32nd or64 or64nd

syntax: l.nop ${uimm16}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-2 f-resv-23-8 f-uimm16

0x5 0x1 0x0 uimm16

semantics:

(c-call VOID "@cpu@_nop" (zext UWI uimm16))

l-or - l.or reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.or $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0x4

semantics:
```
(set rD (or UDI rA rB))
```

l-ori - l.or reg/reg/uimm16

machines: or32 or32nd or64 or64nd

syntax: l.ori $rD,$rA,$uimm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-uimm16

0x2a rD rA uimm16

semantics:
```
(set rD (or UDI rA (zext UWI uimm16)))
```

l-psync - pipeline sync

machines: or32 or32nd or64 or64nd

syntax: l.psync

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-resv-20-21

0x8 0x14 0x0

semantics:
```
(nop)
```

l-rfe - return from exception

machines: or32 or32nd or64 or64nd

syntax: l.rfe

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-resv-25-26

0x9 0x0

semantics:
```
(c-call VOID "@cpu@_rfe")
```

l-ror - l.ror reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.ror $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-2	f-resv-5-2	f-op-3-4
0x38	rD	rA	rB	0x0	0x3	0x0	0x8

semantics:
```
(set rD (ror UDI rA rB))
```

l-rori - l.ror reg/reg/uimm6

machines: or32 or32nd or64 or64nd

syntax: l.rori $rD,$rA,${uimm6}

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6	5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-8	f-op-7-2	f-uimm6
0x2e	rD	rA	0x0	0x3	uimm6

semantics:
```
(set rD (ror UDI rA uimm6))
```

l-sb - l.sb simm16(reg)/reg

machines: or32 or32nd or64 or64nd

syntax: l.sb ${simm16-split}($rA),$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r2 f-r3 f-simm16-split

0x36 rA rB simm16-split

semantics:

(sequence
  ((SI addr))
  (set addr
       (c-call
         AI
         "@cpu@_make_load_store_addr"
         rA
         (ext SI simm16-split)
         1))
  (set (mem UQI addr) (trunc UQI rB))
  (if (eq (and SI addr 268435452) atomic-address)
      (set atomic-reserve 0)))

l-sfeq - l.eq reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfeq $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0x0 rA rB 0x0

semantics:
```
(set sys-sr-f (eq rA rB))
```

l-sfeqi - l.sfeqi reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfeqi $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0x0 rA simm16

semantics:
```
(set sys-sr-f (eq rA (ext WI simm16)))
```

l-sfges - l.sfges reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfges $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0xb rA rB 0x0

semantics:
```
(set sys-sr-f (ge rA rB))
```

l-sfgesi - l.sfgesi reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfgesi $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0xb rA simm16

semantics:
```
(set sys-sr-f (ge rA (ext WI simm16)))
```

l-sfgeu - l.sfgeu reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfgeu $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0x3 rA rB 0x0

semantics:
```
(set sys-sr-f (geu rA rB))
```

l-sfgeui - l.sfgeui reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfgeui $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0x3 rA simm16

semantics:

(set sys-sr-f (geu rA (ext WI simm16)))

l-sfgts - l.sfgts reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfgts $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0xa rA rB 0x0

semantics:
```
(set sys-sr-f (gt rA rB))
```

l-sfgtsi - l.sfgtsi reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfgtsi $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0xa rA simm16

semantics:
```
(set sys-sr-f (gt rA (ext WI simm16)))
```

l-sfgtu - l.sfgtu reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfgtu $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0x2 rA rB 0x0

semantics:
```
(set sys-sr-f (gtu rA rB))
```

l-sfgtui - l.sfgtui reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfgtui $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0x2 rA simm16

semantics:

(set sys-sr-f (gtu rA (ext WI simm16)))

l-sfles - l.sfles reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfles $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0xd rA rB 0x0

semantics:
```
(set sys-sr-f (le rA rB))
```

l-sflesi - l.sflesi reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sflesi $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0xd rA simm16

semantics:
```
(set sys-sr-f (le rA (ext WI simm16)))
```

l-sfleu - l.sfleu reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfleu $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0x5 rA rB 0x0

semantics:
```
(set sys-sr-f (leu rA rB))
```

l-sfleui - l.sfleui reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfleui $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0x5 rA simm16

semantics:

(set sys-sr-f (leu rA (ext WI simm16)))

l-sflts - l.sflts reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sflts $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0xc rA rB 0x0

semantics:
```
(set sys-sr-f (lt rA rB))
```

l-sfltsi - l.sfltsi reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfltsi $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0xc rA simm16

semantics:
```
(set sys-sr-f (lt rA (ext WI simm16)))
```

l-sfltu - l.sfltu reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfltu $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0x4 rA rB 0x0

semantics:
```
(set sys-sr-f (ltu rA rB))
```

l-sfltui - l.sfltui reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfltui $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0x4 rA simm16

semantics:

(set sys-sr-f (ltu rA (ext WI simm16)))

l-sfne - l.ne reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sfne $rA,$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-r3 f-resv-10-11

0x39 0x1 rA rB 0x0

semantics:
```
(set sys-sr-f (ne rA rB))
```

l-sfnei - l.sfnei reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.sfnei $rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-r2 f-simm16

0x2f 0x1 rA simm16

semantics:
```
(set sys-sr-f (ne rA (ext WI simm16)))
```

l-sh - l.sh simm16(reg)/reg

machines: or32 or32nd or64 or64nd

syntax: l.sh ${simm16-split}($rA),$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r2 f-r3 f-simm16-split

0x37 rA rB simm16-split

semantics:

(sequence
  ((SI addr))
  (set addr
       (c-call
         AI
         "@cpu@_make_load_store_addr"
         rA
         (ext SI simm16-split)
         2))
  (set (mem UHI addr) (trunc UHI rB))
  (if (eq (and SI addr 268435452) atomic-address)
      (set atomic-reserve 0)))

l-sll - l.sll reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sll $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-2	f-resv-5-2	f-op-3-4
0x38	rD	rA	rB	0x0	0x0	0x0	0x8

semantics:
```
(set rD (sll UDI rA rB))
```

l-slli - l.sll reg/reg/uimm6

machines: or32 or32nd or64 or64nd

syntax: l.slli $rD,$rA,${uimm6}

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6	5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-8	f-op-7-2	f-uimm6
0x2e	rD	rA	0x0	0x0	uimm6

semantics:
```
(set rD (sll UDI rA uimm6))
```

l-sra - l.sra reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sra $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-2	f-resv-5-2	f-op-3-4
0x38	rD	rA	rB	0x0	0x2	0x0	0x8

semantics:
```
(set rD (sra UDI rA rB))
```

l-srai - l.sra reg/reg/uimm6

machines: or32 or32nd or64 or64nd

syntax: l.srai $rD,$rA,${uimm6}

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6	5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-8	f-op-7-2	f-uimm6
0x2e	rD	rA	0x0	0x2	uimm6

semantics:
```
(set rD (sra UDI rA uimm6))
```

l-srl - l.srl reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.srl $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6	5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-2	f-resv-5-2	f-op-3-4
0x38	rD	rA	rB	0x0	0x1	0x0	0x8

semantics:
```
(set rD (srl UDI rA rB))
```

l-srli - l.srl reg/reg/uimm6

machines: or32 or32nd or64 or64nd

syntax: l.srli $rD,$rA,${uimm6}

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8	7 6	5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-resv-15-8	f-op-7-2	f-uimm6
0x2e	rD	rA	0x0	0x1	uimm6

semantics:
```
(set rD (srl UDI rA uimm6))
```

l-sub - l.sub reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.sub $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0x2

semantics:

(sequence
  ()
  (sequence
    ()
    (set sys-sr-cy (subc-cflag WI rA rB 0))
    (set sys-sr-ov (subc-oflag WI rA rB 0))
    (set rD (sub WI rA rB)))
  (if (andif sys-sr-ov sys-sr-ove)
      (c-call
        VOID
        "@cpu@_exception"
        pc
        (enum INT EXCEPT-RANGE))))

l-sw - l.sw simm16(reg)/reg

machines: or32 or32nd or64 or64nd

syntax: l.sw ${simm16-split}($rA),$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r2 f-r3 f-simm16-split

0x35 rA rB simm16-split

semantics:

(sequence
  ((SI addr))
  (set addr
       (c-call
         AI
         "@cpu@_make_load_store_addr"
         rA
         (ext SI simm16-split)
         4))
  (set (mem USI addr) (trunc USI rB))
  (if (eq (and SI addr 268435452) atomic-address)
      (set atomic-reserve 0)))

l-swa - l.swa simm16(reg)/reg

machines: or32 or32nd or64 or64nd

syntax: l.swa ${simm16-split}($rA),$rB

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r2 f-r3 f-simm16

0x33 rA rB simm16

semantics:

(sequence
  ((SI addr) (BI flag))
  (set addr
       (c-call
         AI
         "@cpu@_make_load_store_addr"
         rA
         (ext SI simm16-split)
         4))
  (set sys-sr-f
       (and BI atomic-reserve (eq addr atomic-address)))
  (if sys-sr-f (set (mem USI addr) (trunc USI rB)))
  (set atomic-reserve 0))

l-sys - syscall (exception)

machines: or32 or32nd or64 or64nd

syntax: l.sys ${uimm16}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-resv-20-5 f-uimm16

0x8 0x0 0x0 uimm16

semantics:

(c-call
  VOID
  "@cpu@_exception"
  pc
  (enum INT EXCEPT-SYSCALL))

l-trap - trap (exception)

machines: or32 or32nd or64 or64nd

syntax: l.trap ${uimm16}

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-op-25-5 f-resv-20-5 f-uimm16

0x8 0x8 0x0 uimm16

semantics:

(c-call
  VOID
  "@cpu@_exception"
  pc
  (enum INT EXCEPT-TRAP))

l-xor - l.xor reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: l.xor $rD,$rA,$rB

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4	3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-7	f-op-3-4
0x38	rD	rA	rB	0x0	0x5

semantics:
```
(set rD (xor UDI rA rB))
```

l-xori - l.xor reg/reg/simm16

machines: or32 or32nd or64 or64nd

syntax: l.xori $rD,$rA,$simm16

format:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f-opcode f-r1 f-r2 f-simm16

0x2b rD rA simm16

semantics:
```
(set rD (xor UDI rA (ext WI simm16)))
```

lf-add-d - lf.add.d reg/reg/reg

machines: or64 or64nd

syntax: lf.add.d $rDDF,$rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rADF	rBDF	0x0	0x10

semantics:
```
(set rDDF (add DF rADF rBDF))
```

lf-add-d32 - lf.add.d regpair/regpair/regpair

machines: or32 or32nd

syntax: lf.add.d $rDD32F,$rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21 20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-rdd32	f-rad32	f-rbd32	f-op-7-8
0x32	rDD32F	rAD32F	rBD32F	0x10

semantics:
```
(set rDD32F (add DF rAD32F rBD32F))
```

lf-add-s - lf.add.s reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.add.s $rDSF,$rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rASF	rBSF	0x0	0x0

semantics:
```
(set rDSF (add SF rASF rBSF))
```

lf-cust1-d - lf.cust1.d

machines: or64 or64nd

syntax: lf.cust1.d

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-resv-25-5	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0xe0

semantics:
```
(nop)
```

lf-cust1-d32 - lf.cust1.d

machines: or32 or32nd

syntax: lf.cust1.d

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-resv-25-5	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0xe0

semantics:
```
(nop)
```

lf-cust1-s - lf.cust1.s

machines: or32 or32nd or64 or64nd

syntax: lf.cust1.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-resv-25-5	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0xd0

semantics:
```
(nop)
```

lf-div-d - lf.div.d reg/reg/reg

machines: or64 or64nd

syntax: lf.div.d $rDDF,$rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rADF	rBDF	0x0	0x13

semantics:
```
(set rDDF (div DF rADF rBDF))
```

lf-div-d32 - lf.div.d regpair/regpair/regpair

machines: or32 or32nd

syntax: lf.div.d $rDD32F,$rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21 20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-rdd32	f-rad32	f-rbd32	f-op-7-8
0x32	rDD32F	rAD32F	rBD32F	0x13

semantics:
```
(set rDD32F (div DF rAD32F rBD32F))
```

lf-div-s - lf.div.s reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.div.s $rDSF,$rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rASF	rBSF	0x0	0x3

semantics:
```
(set rDSF (div SF rASF rBSF))
```

lf-ftoi-d - lf.ftoi.d reg/reg

machines: or64 or64nd

syntax: lf.ftoi.d $rD,$rADF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rD	rADF	0x0	0x0	0x15

semantics:

(set rD
     (fix WI
          (case INT
                sys-fpcsr-rm
                ((0) 1)
                ((1) 3)
                ((2) 4)
                (else 5))
          rADF))

lf-ftoi-d32 - lf.ftoi.d regpair/regpair

machines: or32 or32nd

syntax: lf.ftoi.d $rDDI,$rAD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16 15	14 13 12 11 10 9	8	7 6 5 4 3 2 1 0
f-opcode	f-r3	f-rdd32	f-rad32	f-resv-8-1	f-op-7-8
0x32	0x0	rDDI	rAD32F	0x0	0x15

semantics:

(set rDDI
     (fix DI
          (case INT
                sys-fpcsr-rm
                ((0) 1)
                ((1) 3)
                ((2) 4)
                (else 5))
          rAD32F))

lf-ftoi-s - lf.ftoi.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.ftoi.s $rD,$rASF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rD	rASF	0x0	0x0	0x5

semantics:

(set rD
     (ext WI
          (fix SI
               (case INT
                     sys-fpcsr-rm
                     ((0) 1)
                     ((1) 3)
                     ((2) 4)
                     (else 5))
               rASF)))

lf-itof-d - lf.itof.d reg/reg

machines: or64 or64nd

syntax: lf.itof.d $rDDF,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rA	0x0	0x0	0x14

semantics:

(set rDDF
     (float DF
            (case INT
                  sys-fpcsr-rm
                  ((0) 1)
                  ((1) 3)
                  ((2) 4)
                  (else 5))
            rA))

lf-itof-d32 - lf.itof.d regpair/regpair

machines: or32 or32nd

syntax: lf.itof.d $rDD32F,$rADI

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16 15	14 13 12 11 10 9	8	7 6 5 4 3 2 1 0
f-opcode	f-r3	f-rdd32	f-rad32	f-resv-8-1	f-op-7-8
0x32	0x0	rDD32F	rADI	0x0	0x14

semantics:

(set rDD32F
     (float DF
            (case INT
                  sys-fpcsr-rm
                  ((0) 1)
                  ((1) 3)
                  ((2) 4)
                  (else 5))
            rADI))

lf-itof-s - lf.itof.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.itof.s $rDSF,$rA

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rA	0x0	0x0	0x4

semantics:

(set rDSF
     (float SF
            (case INT
                  sys-fpcsr-rm
                  ((0) 1)
                  ((1) 3)
                  ((2) 4)
                  (else 5))
            (trunc SI rA)))

lf-madd-d - lf.madd.d reg/reg/reg

machines: or64 or64nd

syntax: lf.madd.d $rDDF,$rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rADF	rBDF	0x0	0x17

semantics:

(set rDDF (add DF (mul DF rADF rBDF) rDDF))

lf-madd-d32 - lf.madd.d regpair/regpair/regpair

machines: or32 or32nd

syntax: lf.madd.d $rDD32F,$rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21 20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-rdd32	f-rad32	f-rbd32	f-op-7-8
0x32	rDD32F	rAD32F	rBD32F	0x17

semantics:

(set rDD32F
     (add DF (mul DF rAD32F rBD32F) rDD32F))

lf-madd-s - lf.madd.s reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.madd.s $rDSF,$rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rASF	rBSF	0x0	0x7

semantics:

(set rDSF (add SF (mul SF rASF rBSF) rDSF))

lf-mul-d - lf.mul.d reg/reg/reg

machines: or64 or64nd

syntax: lf.mul.d $rDDF,$rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rADF	rBDF	0x0	0x12

semantics:
```
(set rDDF (mul DF rADF rBDF))
```

lf-mul-d32 - lf.mul.d regpair/regpair/regpair

machines: or32 or32nd

syntax: lf.mul.d $rDD32F,$rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21 20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-rdd32	f-rad32	f-rbd32	f-op-7-8
0x32	rDD32F	rAD32F	rBD32F	0x12

semantics:
```
(set rDD32F (mul DF rAD32F rBD32F))
```

lf-mul-s - lf.mul.s reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.mul.s $rDSF,$rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rASF	rBSF	0x0	0x2

semantics:
```
(set rDSF (mul SF rASF rBSF))
```

lf-rem-d - lf.rem.d reg/reg/reg

machines: or64 or64nd

syntax: lf.rem.d $rDDF,$rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rADF	rBDF	0x0	0x16

semantics:
```
(set rDDF (rem DF rADF rBDF))
```

lf-rem-d32 - lf.rem.d regpair/regpair/regpair

machines: or32 or32nd

syntax: lf.rem.d $rDD32F,$rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21 20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-rdd32	f-rad32	f-rbd32	f-op-7-8
0x32	rDD32F	rAD32F	rBD32F	0x16

semantics:
```
(set rDD32F (rem DF rAD32F rBD32F))
```

lf-rem-s - lf.rem.s reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.rem.s $rDSF,$rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rASF	rBSF	0x0	0x6

semantics:
```
(set rDSF (rem SF rASF rBSF))
```

lf-sfeq-d - lf.sfeq.d reg/reg

machines: or64 or64nd

syntax: lf.sfeq.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x18

semantics:
```
(set sys-sr-f (eq rADF rBDF))
```

lf-sfeq-d32 - lf.sfeq.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfeq.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x18

semantics:
```
(set sys-sr-f (eq rAD32F rBD32F))
```

lf-sfeq-s - lf.sfeq.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfeq.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x8

semantics:
```
(set sys-sr-f (eq rASF rBSF))
```

lf-sfge-d - lf.sfge.d reg/reg

machines: or64 or64nd

syntax: lf.sfge.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x1b

semantics:
```
(set sys-sr-f (ge rADF rBDF))
```

lf-sfge-d32 - lf.sfge.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfge.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x1b

semantics:
```
(set sys-sr-f (ge rAD32F rBD32F))
```

lf-sfge-s - lf.sfge.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfge.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0xb

semantics:
```
(set sys-sr-f (ge rASF rBSF))
```

lf-sfgt-d - lf.sfgt.d reg/reg

machines: or64 or64nd

syntax: lf.sfgt.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x1a

semantics:
```
(set sys-sr-f (gt rADF rBDF))
```

lf-sfgt-d32 - lf.sfgt.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfgt.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x1a

semantics:
```
(set sys-sr-f (gt rAD32F rBD32F))
```

lf-sfgt-s - lf.sfgt.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfgt.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0xa

semantics:
```
(set sys-sr-f (gt rASF rBSF))
```

lf-sfle-d - lf.sfle.d reg/reg

machines: or64 or64nd

syntax: lf.sfle.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x1d

semantics:
```
(set sys-sr-f (le rADF rBDF))
```

lf-sfle-d32 - lf.sfle.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfle.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x1d

semantics:
```
(set sys-sr-f (le rAD32F rBD32F))
```

lf-sfle-s - lf.sfle.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfle.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0xd

semantics:
```
(set sys-sr-f (le rASF rBSF))
```

lf-sflt-d - lf.sflt.d reg/reg

machines: or64 or64nd

syntax: lf.sflt.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x1c

semantics:
```
(set sys-sr-f (lt rADF rBDF))
```

lf-sflt-d32 - lf.sflt.d regpair/regpair

machines: or32 or32nd

syntax: lf.sflt.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x1c

semantics:
```
(set sys-sr-f (lt rAD32F rBD32F))
```

lf-sflt-s - lf.sflt.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sflt.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0xc

semantics:
```
(set sys-sr-f (lt rASF rBSF))
```

lf-sfne-d - lf.sfne.d reg/reg

machines: or64 or64nd

syntax: lf.sfne.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x19

semantics:
```
(set sys-sr-f (ne rADF rBDF))
```

lf-sfne-d32 - lf.sfne.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfne.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x19

semantics:
```
(set sys-sr-f (ne rAD32F rBD32F))
```

lf-sfne-s - lf.sfne.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfne.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x9

semantics:
```
(set sys-sr-f (ne rASF rBSF))
```

lf-sfueq-d - lf.sfueq.d reg/reg

machines: or64 or64nd

syntax: lf.sfueq.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x38

semantics:

(set sys-sr-f
     (or BI (unordered DF rADF rBDF) (eq rADF rBDF)))

lf-sfueq-d32 - lf.sfueq.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfueq.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x38

semantics:

(set sys-sr-f
     (or BI
         (unordered DF rAD32F rBD32F)
         (eq rAD32F rBD32F)))

lf-sfueq-s - lf.sfueq.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfueq.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x28

semantics:

(set sys-sr-f
     (or BI (unordered SF rASF rBSF) (eq rASF rBSF)))

lf-sfuge-d - lf.sfuge.d reg/reg

machines: or64 or64nd

syntax: lf.sfuge.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x3b

semantics:

(set sys-sr-f
     (or BI (unordered DF rADF rBDF) (ge rADF rBDF)))

lf-sfuge-d32 - lf.sfuge.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfuge.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x3b

semantics:

(set sys-sr-f
     (or BI
         (unordered DF rAD32F rBD32F)
         (ge rAD32F rBD32F)))

lf-sfuge-s - lf.sfuge.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfuge.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x2b

semantics:

(set sys-sr-f
     (or BI (unordered SF rASF rBSF) (ge rASF rBSF)))

lf-sfugt-d - lf.sfugt.d reg/reg

machines: or64 or64nd

syntax: lf.sfugt.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x3a

semantics:

(set sys-sr-f
     (or BI (unordered DF rADF rBDF) (gt rADF rBDF)))

lf-sfugt-d32 - lf.sfugt.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfugt.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x3a

semantics:

(set sys-sr-f
     (or BI
         (unordered DF rAD32F rBD32F)
         (gt rAD32F rBD32F)))

lf-sfugt-s - lf.sfugt.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfugt.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x2a

semantics:

(set sys-sr-f
     (or BI (unordered SF rASF rBSF) (gt rASF rBSF)))

lf-sfule-d - lf.sfule.d reg/reg

machines: or64 or64nd

syntax: lf.sfule.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x3d

semantics:

(set sys-sr-f
     (or BI (unordered DF rADF rBDF) (le rADF rBDF)))

lf-sfule-d32 - lf.sfule.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfule.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x3d

semantics:

(set sys-sr-f
     (or BI
         (unordered DF rAD32F rBD32F)
         (le rAD32F rBD32F)))

lf-sfule-s - lf.sfule.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfule.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x2d

semantics:

(set sys-sr-f
     (or BI (unordered SF rASF rBSF) (le rASF rBSF)))

lf-sfult-d - lf.sfult.d reg/reg

machines: or64 or64nd

syntax: lf.sfult.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x3c

semantics:

(set sys-sr-f
     (or BI (unordered DF rADF rBDF) (lt rADF rBDF)))

lf-sfult-d32 - lf.sfult.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfult.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x3c

semantics:

(set sys-sr-f
     (or BI
         (unordered DF rAD32F rBD32F)
         (lt rAD32F rBD32F)))

lf-sfult-s - lf.sfult.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfult.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x2c

semantics:

(set sys-sr-f
     (or BI (unordered SF rASF rBSF) (lt rASF rBSF)))

lf-sfun-d - lf.sfun.d reg/reg

machines: or64 or64nd

syntax: lf.sfun.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x3e

semantics:

(set sys-sr-f (unordered DF rADF rBDF))

lf-sfun-d32 - lf.sfun.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfun.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x3e

semantics:

(set sys-sr-f (unordered DF rAD32F rBD32F))

lf-sfun-s - lf.sfun.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfun.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x2e

semantics:

(set sys-sr-f (unordered SF rASF rBSF))

lf-sfune-d - lf.sfune.d reg/reg

machines: or64 or64nd

syntax: lf.sfune.d $rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rADF	rBDF	0x0	0x39

semantics:

(set sys-sr-f
     (or BI (unordered DF rADF rBDF) (ne rADF rBDF)))

lf-sfune-d32 - lf.sfune.d regpair/regpair

machines: or32 or32nd

syntax: lf.sfune.d $rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21	20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-10-1	f-rad32	f-rbd32	f-op-7-8
0x32	0x0	0x0	rAD32F	rBD32F	0x39

semantics:

(set sys-sr-f
     (or BI
         (unordered DF rAD32F rBD32F)
         (ne rAD32F rBD32F)))

lf-sfune-s - lf.sfune.s reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sfune.s $rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	0x0	rASF	rBSF	0x0	0x29

semantics:

(set sys-sr-f
     (or BI (unordered SF rASF rBSF) (ne rASF rBSF)))

lf-sub-d - lf.sub.d reg/reg/reg

machines: or64 or64nd

syntax: lf.sub.d $rDDF,$rADF,$rBDF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDDF	rADF	rBDF	0x0	0x11

semantics:
```
(set rDDF (sub DF rADF rBDF))
```

lf-sub-d32 - lf.sub.d regpair/regpair/regpair

machines: or32 or32nd

syntax: lf.sub.d $rDD32F,$rAD32F,$rBD32F

format:

31 30 29 28 27 26	25 24 23 22 21 20	19 18 17 16 15 14	13 12 11 10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-rdd32	f-rad32	f-rbd32	f-op-7-8
0x32	rDD32F	rAD32F	rBD32F	0x11

semantics:
```
(set rDD32F (sub DF rAD32F rBD32F))
```

lf-sub-s - lf.sub.s reg/reg/reg

machines: or32 or32nd or64 or64nd

syntax: lf.sub.s $rDSF,$rASF,$rBSF

format:

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11	10 9 8	7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-r3	f-resv-10-3	f-op-7-8
0x32	rDSF	rASF	rBSF	0x0	0x1

semantics:
```
(set rDSF (sub SF rASF rBSF))
```

Macro Instructions

Macro instructions for each machine:

or32 - Generic OpenRISC 1000 32-bit CPU
or32nd - Generic OpenRISC 1000 32-bit CPU with no branch delay slot
or64 - Generic OpenRISC 1000 64-bit CPU
or64nd - Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot

or32 - Generic OpenRISC 1000 32-bit CPU

or32nd - Generic OpenRISC 1000 32-bit CPU with no branch delay slot

or64 - Generic OpenRISC 1000 64-bit CPU

or64nd - Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot

Individual macro-instructions descriptions

This documentation was machine generated from the cgen cpu description files for this architecture.
https://sourceware.org/cgen/

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-r1	f-disp21
0x2	rD	disp21

31 30 29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-disp26
0x4	disp26

31 30 29 28 27 26	25 24 23 22 21 20 19 18 17 16	15 14 13 12 11	10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-resv-25-10	f-r3	f-resv-10-11
0x12	0x0	rB	0x0

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17	16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-r1	f-resv-20-4	f-op-16-1	f-uimm16
0x6	rD	0x0	0x1	0x0

31 30 29 28 27 26	25 24	23 22 21 20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-op-25-2	f-resv-23-8	f-uimm16
0x5	0x1	0x0	uimm16

31 30 29 28 27 26	25 24 23 22 21	20 19 18 17 16	15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-r1	f-r2	f-simm16
0x27	rD	rA	simm16

31 30 29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-resv-25-26
0x1e	0x0

31 30 29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-resv-25-26
0x1f	0x0

31 30 29 28 27 26	25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f-opcode	f-resv-25-26
0x3f	0x0

Instructions

or32 MEM - Memory

or32 ALU - ALU

or32 FPU - FPU

or32 BR - Branch

or32 or32 - Generic OpenRISC 1000 32-bit CPU

or32nd MEM - Memory

or32nd ALU - ALU

or32nd FPU - FPU

or32nd BR - Branch

or32nd or32nd - Generic OpenRISC 1000 32-bit CPU with no branch delay slot

or64 MEM - Memory

or64 ALU - ALU

or64 FPU - FPU

or64 BR - Branch

or64 or64 - Generic OpenRISC 1000 64-bit CPU

or64nd MEM - Memory

or64nd ALU - ALU

or64nd FPU - FPU

or64nd BR - Branch

or64nd or64nd - Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot

Individual instructions descriptions

l-add - l.add reg/reg/reg

l-addc - l.addc reg/reg/reg

l-addi - l.addi reg/reg/simm16

l-addic - l.addic reg/reg/simm16

l-adrp - adrp reg/disp21

l-and - l.and reg/reg/reg

l-andi - l.and reg/reg/uimm16

l-bf - branch if condition bit set (pc relative iaddr)

l-bnf - branch if condition bit not set (pc relative iaddr)

l-cmov - l.cmov reg/reg/reg

l-csync - context sync

l-cust1 - l.cust1

l-cust2 - l.cust2

l-cust3 - l.cust3

l-cust4 - l.cust4

l-cust5 - l.cust5

l-cust6 - l.cust6

l-cust7 - l.cust7

l-cust8 - l.cust8

l-div - divide (signed)

l-divu - divide (unsigned)

l-extbs - l.extbs reg/reg

l-extbz - l.extbz reg/reg

l-exths - l.exths reg/reg

l-exthz - l.exthz reg/reg

l-extws - l.extws reg/reg

l-extwz - l.extwz reg/reg

l-ff1 - find first '1'

l-fl1 - find last '1'

l-j - jump (pc-relative iaddr)

l-jal - jump and link (pc-relative iaddr)

l-jalr - jump register and link (absolute iaddr)

l-jr - jump register (absolute iaddr)

l-lbs - l.lbs reg/simm16(reg)

l-lbz - l.lbz reg/simm16(reg)

l-lhs - l.lhs reg/simm16(reg)

l-lhz - l.lhz reg/simm16(reg)

l-lwa - l.lwa reg/simm16(reg)

l-lws - l.lws reg/simm16(reg)

l-lwz - l.lwz reg/simm16(reg)

l-mac - l.mac reg/reg

l-maci - l.maci reg/simm16

l-macrc - macrc reg

l-macu - l.macu reg/reg

l-mfspr - mfspr

l-movhi - movhi reg/uimm16

l-msb - l.msb reg/reg

l-msbu - l.msbu reg/reg

l-msync - memory sync

l-mtspr - mtspr

l-mul - l.mul reg/reg/reg

l-muld - l.muld reg/reg

l-muldu - l.muld reg/reg

l-muli - l.muli reg/reg/simm16

l-mulu - l.mulu reg/reg/reg

l-nop - nop

l-nop-imm - nop uimm16

l-or - l.or reg/reg/reg