Instructions

• playb - experimental mach
• MEM - Memory
• ALU - ALU
• FPU - FPU
• alphabetically

playb MEM - Memory

• ld - ld
• ldb - ldb
• ldh - ldh
• ldub - ldub
• lduh - lduh
• load-df - use df
• load-tf - use tf
• make-df - use df

playb ALU - ALU

• add - add
• addi16 - addi16
• addi32 - addi32
• addv2 - add version 2
• do-count-test - do-count-test
• ldm - ldm
• use-ifield - use-ifield
• use-index-of - index-of

playb FPU - FPU

• make-tf - use tf
• split-df - use df
• split-tf - use tf

playb playb - experimental mach

• add - add
• addi16 - addi16
• addi32 - addi32
• addv2 - add version 2
• do-count-test - do-count-test
• ld - ld
• ldb - ldb
• ldh - ldh
• ldm - ldm
• ldub - ldub
• lduh - lduh
• load-df - use df
• load-tf - use tf
• make-df - use df
• make-tf - use tf
• split-df - use df
• split-tf - use tf
• use-ifield - use-ifield
• use-index-of - index-of

Individual instructions descriptions

add - add

• machines: base


• syntax: add $dr,$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x4	0x0	dr	sr



• semantics:

  (sequence
    ()
    (set vbit (add-oflag SI dr sr 0))
    (set cbit (add-cflag SI dr sr 0))
    (set dr (add SI dr sr))
    (set zbit (eq dr 0))
    (set nbit (lt dr 0)))
  

addi16 - addi16

• machines: base


• syntax: addi16 $dr,$sr,$simm16


• format:

  31 30 29 28	27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-simm16	f-op2	f-r1	f-r2
  0x4	simm16	0x2	dr	sr



• semantics:

  (set dr (add SI sr simm16))
  

addi32 - addi32

• machines: base


• syntax: addi32 $dr,$sr,$simm32


• format:

  47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16	15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-simm32	f-op1	f-op2	f-r1	f-r2
  simm32	0x4	0x3	dr	sr



• semantics:

  (set dr (add SI sr simm32))
  

addv2 - add version 2

• machines: base


• syntax: add $dr,$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x4	0x1	dr	sr



• semantics:

  (sequence
    ((WI tmp1))
    (parallel
      ()
      (set tmp1 (add SI dr sr))
      (set vbit (add-oflag SI dr sr 0))
      (set cbit (add-cflag SI dr sr 0)))
    (set zbit (eq tmp1 0))
    (set nbit (lt tmp1 0))
    (set dr tmp1))
  

do-count-test - do-count-test

• machines: base


• syntax: do-count-test $dr,$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x7	0x0	dr	sr



• semantics:

  (sequence
    ()
    (do-count VOID iter 4 (set dr (add SI sr iter)))
    (do-count
      VOID
      iter
      (and SI sr 7)
      (set dr (add SI sr iter))))
  

ld - ld

• machines: base


• syntax: ld $dr,@@$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x2	0xc	dr	sr



• semantics:

  (set dr (mem WI sr))
  

ldb - ldb

• machines: base


• syntax: ldb $dr,@@$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x2	0x8	dr	sr



• semantics:

  (set dr (ext WI (mem QI sr)))
  

ldh - ldh

• machines: base


• syntax: ldh $dr,@@$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x2	0xa	dr	sr



• semantics:

  (set dr (ext WI (mem HI sr)))
  

ldm - ldm

• machines: base


• syntax: ldm $dr,$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x5	0x2	dr	sr



• semantics:

  (sequence
    ()
    (set dr sr)
    (set (reg SI h-gr (add INT (index-of dr) 1))
         (reg SI h-gr (add INT (index-of sr) 1))))
  

ldub - ldub

• machines: base


• syntax: ldub $dr,@@$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x2	0x9	dr	sr



• semantics:

  (set dr (zext WI (mem QI sr)))
  

lduh - lduh

• machines: base


• syntax: lduh $dr,@@$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x2	0xb	dr	sr



• semantics:

  (set dr (zext WI (mem HI sr)))
  

load-df - use df

• machines: base


• syntax: load-df df,[$sr]


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-op3	f-r2
  0x6	0x0	0x0	sr



• semantics:

  (set df-reg (mem DF sr))
  

load-tf - use tf

• machines: base


• syntax: load-tf tf,[$sr]


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-op3	f-r2
  0x6	0x3	0x0	sr



• semantics:

  (set tf-reg (mem TF sr))
  

make-df - use df

• machines: base


• syntax: make-df df,[$sr]


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-op3	f-r2
  0x6	0x1	0x0	sr



• semantics:

  (set df-reg
       (join DF SI (mem SI sr) (mem SI (add SI sr 4))))
  

make-tf - use tf

• machines: base


• syntax: make-tf tf,[$sr]


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-op3	f-r2
  0x6	0x4	0x0	sr



• semantics:

  (set tf-reg
       (join TF
             SI
             sr
             (reg SI h-gr (add INT (index-of sr) 1))
             (reg SI h-gr (add INT (index-of sr) 2))
             (reg SI h-gr (add INT (index-of sr) 3))))
  

split-df - use df

• machines: base


• syntax: split-df df,[$sr]


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-op3	f-r2
  0x6	0x2	0x0	sr



• semantics:

  (sequence
    ((DF temp))
    (set temp df-reg)
    (set 0 0))
  

split-tf - use tf

• machines: base


• syntax: split-tf tf,[$sr]


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-op3	f-r2
  0x6	0x5	0x0	sr



• semantics:

  (sequence
    ((TF temp))
    (set temp tf-reg)
    (set 0 0))
  

use-ifield - use-ifield

• machines: base


• syntax: foo $dr,$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x5	0x3	dr	sr



• semantics:

  (sequence () (set dr f-r2))
  

use-index-of - index-of

• machines: base


• syntax: index-of $dr,$sr


• format:

  15 14 13 12	11 10 9 8	7 6 5 4	3 2 1 0
  f-op1	f-op2	f-r1	f-r2
  0x5	0x4	dr	sr



• semantics:

  (set dr (reg SI h-gr (add INT (index-of sr) 1)))
  

Macro Instructions

• playb - experimental mach

playb - experimental mach

Individual macro-instructions descriptions

This documentation was machine generated from the cgen cpu description files for this architecture.
https://sourceware.org/cgen/