15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x4 | 0x0 | dr | sr |
(sequence () (set vbit (add-oflag SI dr sr 0)) (set cbit (add-cflag SI dr sr 0)) (set dr (add SI dr sr)) (set zbit (eq dr 0)) (set nbit (lt dr 0)))
31 30 29 28 | 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-simm16 | f-op2 | f-r1 | f-r2 |
0x4 | simm16 | 0x2 | dr | sr |
(set dr (add SI sr simm16))
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-simm32 | f-op1 | f-op2 | f-r1 | f-r2 |
simm32 | 0x4 | 0x3 | dr | sr |
(set dr (add SI sr simm32))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x4 | 0x1 | dr | sr |
(sequence ((WI tmp1)) (parallel () (set tmp1 (add SI dr sr)) (set vbit (add-oflag SI dr sr 0)) (set cbit (add-cflag SI dr sr 0))) (set zbit (eq tmp1 0)) (set nbit (lt tmp1 0)) (set dr tmp1))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x7 | 0x0 | dr | sr |
(sequence () (do-count VOID iter 4 (set dr (add SI sr iter))) (do-count VOID iter (and SI sr 7) (set dr (add SI sr iter))))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x2 | 0xc | dr | sr |
(set dr (mem WI sr))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x2 | 0x8 | dr | sr |
(set dr (ext WI (mem QI sr)))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x2 | 0xa | dr | sr |
(set dr (ext WI (mem HI sr)))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x5 | 0x2 | dr | sr |
(sequence () (set dr sr) (set (reg SI h-gr (add INT (index-of dr) 1)) (reg SI h-gr (add INT (index-of sr) 1))))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x2 | 0x9 | dr | sr |
(set dr (zext WI (mem QI sr)))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x2 | 0xb | dr | sr |
(set dr (zext WI (mem HI sr)))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-op3 | f-r2 |
0x6 | 0x0 | 0x0 | sr |
(set df-reg (mem DF sr))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-op3 | f-r2 |
0x6 | 0x3 | 0x0 | sr |
(set tf-reg (mem TF sr))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-op3 | f-r2 |
0x6 | 0x1 | 0x0 | sr |
(set df-reg (join DF SI (mem SI sr) (mem SI (add SI sr 4))))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-op3 | f-r2 |
0x6 | 0x4 | 0x0 | sr |
(set tf-reg (join TF SI sr (reg SI h-gr (add INT (index-of sr) 1)) (reg SI h-gr (add INT (index-of sr) 2)) (reg SI h-gr (add INT (index-of sr) 3))))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-op3 | f-r2 |
0x6 | 0x2 | 0x0 | sr |
(sequence ((DF temp)) (set temp df-reg) (set 0 0))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-op3 | f-r2 |
0x6 | 0x5 | 0x0 | sr |
(sequence ((TF temp)) (set temp tf-reg) (set 0 0))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x5 | 0x3 | dr | sr |
(sequence () (set dr f-r2))
15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
f-op1 | f-op2 | f-r1 | f-r2 |
0x5 | 0x4 | dr | sr |
(set dr (reg SI h-gr (add INT (index-of sr) 1)))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/