0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x10a | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set alu-ov (add-oflag SI ra rb 0)) (set alu-ca (add-cflag SI ra rb 0)) (set rd (addc SI ra rb 0))) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0xa | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI ra rb 0)) (set alu-ca (add-cflag SI ra rb 0)) (set rd (addc SI ra rb 0))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x8a | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI ra rb xer-ca)) (set alu-ca (add-cflag SI ra rb xer-ca)) (set rd (addc SI ra rb xer-ca))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-simm |
0xe | rd | ra | simm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set alu-ov (add-oflag WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) simm 0)) (set alu-ca (add-cflag WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) simm 0)) (set rd (addc WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) simm 0))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-simm |
0xc | rd | ra | simm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI ra simm 0)) (set alu-ca (add-cflag SI ra simm 0)) (set rd (addc SI ra simm 0))) (set-quiet xer-ca alu-ca)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-simm |
0xd | rd | ra | simm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI ra simm 0)) (set alu-ca (add-cflag SI ra simm 0)) (set rd (addc SI ra simm 0))) (set-quiet xer-ca alu-ca) (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-simm |
0xf | rd | ra | simm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set alu-ov (add-oflag WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) (sll INT simm 16) 0)) (set alu-ca (add-cflag WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) (sll INT simm 16) 0)) (set rd (addc WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) (sll INT simm 16) 0))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | 0x0 | oe | 0xea | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI ra -1 xer-ca)) (set alu-ca (add-cflag SI ra -1 xer-ca)) (set rd (addc SI ra -1 xer-ca))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | 0x0 | oe | 0xca | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI ra 0 xer-ca)) (set alu-ca (add-cflag SI ra 0 xer-ca)) (set rd (addc SI ra 0 xer-ca))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x1c | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (and SI rs rb)) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x3c | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (and SI rs (inv SI rb))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-uimm |
0x1c | rs | ra | uimm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set ra (and SI rs uimm)) (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-uimm |
0x1d | rs | ra | uimm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set ra (and SI rs (sll UINT uimm 16))) (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 | 31 |
f-opcd | f-li | f-aa | f-lk |
0x12 | li | aa | lk |
(sequence () (if lk (set lr (add USI pc 4))) (set pc (cond IAI ((eq f-aa 1) (sll USI li 2)) (else add USI pc (sll USI li 2)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 | 30 | 31 |
f-opcd | f-bo | f-bi | f-bd | f-aa | f-lk |
0x10 | bo | bi | bd | aa | lk |
(sequence () (sequence ((INT cond_ok) (INT ctr_ok)) (if (not UINT (and UINT (srl UINT bo 2) 1)) (set ctr (sub SI ctr 1))) (set ctr_ok (c-call INT "@cpu@_cti_resolv_ctr" bo bi)) (set cond_ok (c-call INT "@cpu@_cti_resolv_cond" bo bi)) (if (andif ctr_ok cond_ok) (sequence () (if lk (set lr (add USI pc 4))) (set pc (cond IAI ((eq f-aa 1) (sll USI bd 2)) (else add USI pc (sll USI bd 2))))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-bo | f-bi | f-rb | f-oe | f-xo | f-lk |
0x13 | bo | bi | 0x0 | 0x0 | 0x210 | lk |
(sequence () (sequence ((INT cond_ok)) (set cond_ok (c-call INT "@cpu@_cti_resolv_cond" bo bi)) (if cond_ok (sequence ((IAI nia)) (set nia ctr) (if lk (set lr (add USI pc 4))) (set pc nia)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-bo | f-bi | f-rb | f-oe | f-xo | f-lk |
0x13 | bo | bi | 0x0 | 0x0 | 0x10 | lk |
(sequence () (sequence ((INT cond_ok) (INT ctr_ok)) (if (not UINT (and UINT (srl UINT bo 2) 1)) (set ctr (sub SI ctr 1))) (set ctr_ok (c-call INT "@cpu@_cti_resolv_ctr" bo bi)) (set cond_ok (c-call INT "@cpu@_cti_resolv_cond" bo bi)) (if (andif ctr_ok cond_ok) (sequence ((IAI nia)) (set nia lr) (if lk (set lr (add USI pc 4))) (set pc nia)))))
0 1 2 3 4 5 | 6 7 8 | 9 | 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crfd | f-res/9-1 | f-l | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | crfd | 0x0 | l | ra | rb | 0x0 | 0x0 | 0x0 |
(set crfd (cond QI ((lt ra rb) 8) ((gt ra rb) 4) (else . 2)))
0 1 2 3 4 5 | 6 7 8 | 9 | 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-crfd | f-res/9-1 | f-l | f-ra | f-simm |
0xb | crfd | 0x0 | l | ra | simm |
(set crfd (cond QI ((lt ra simm) 8) ((gt ra simm) 4) (else . 2)))
0 1 2 3 4 5 | 6 7 8 | 9 | 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crfd | f-res/9-1 | f-l | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | crfd | 0x0 | l | ra | rb | 0x0 | 0x20 | 0x0 |
(set crfd (cond QI ((ltu ra rb) 8) ((gtu ra rb) 4) (else . 2)))
0 1 2 3 4 5 | 6 7 8 | 9 | 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-crfd | f-res/9-1 | f-l | f-ra | f-uimm |
0xa | crfd | 0x0 | l | ra | uimm |
(set crfd (cond QI ((ltu ra uimm) 8) ((gtu ra uimm) 4) (else . 2)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0x101 | 0x0 |
(sequence ((BI result)) (set result (and SI (and SI (srl SI (reg SI h-cr) crba) 1) (and SI (srl SI (reg SI h-cr) crbb) 1))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0x81 | 0x0 |
(sequence ((BI result)) (set result (and SI (and SI (srl SI (reg SI h-cr) crba) 1) (inv SI (and SI (srl SI (reg SI h-cr) crbb) 1)))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0x121 | 0x0 |
(sequence ((BI result)) (set result (not SI (xor SI (and SI (srl SI (reg SI h-cr) crba) 1) (and SI (srl SI (reg SI h-cr) crbb) 1)))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0xe1 | 0x0 |
(sequence ((BI result)) (set result (inv SI (and SI (and SI (srl SI (reg SI h-cr) crba) 1) (and SI (srl SI (reg SI h-cr) crbb) 1)))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0x21 | 0x0 |
(sequence ((BI result)) (set result (inv SI (or SI (and SI (srl SI (reg SI h-cr) crba) 1) (and SI (srl SI (reg SI h-cr) crbb) 1)))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0x1c1 | 0x0 |
(sequence ((BI result)) (set result (or SI (and SI (srl SI (reg SI h-cr) crba) 1) (and SI (srl SI (reg SI h-cr) crbb) 1))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0x1a1 | 0x0 |
(sequence ((BI result)) (set result (or SI (and SI (srl SI (reg SI h-cr) crba) 1) (inv SI (and SI (srl SI (reg SI h-cr) crbb) 1)))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crbd | f-crba | f-crbb | f-oe | f-xo | f-rc |
0x13 | crbd | crba | crbb | 0x0 | 0xc1 | 0x0 |
(sequence ((BI result)) (set result (xor SI (and SI (srl SI (reg SI h-cr) crba) 1) (and SI (srl SI (reg SI h-cr) crbb) 1))) (if result (set (reg SI h-cr) (or SI (reg SI h-cr) (sll SI 1 crbd))) (set (reg SI h-cr) (and SI (reg SI h-cr) (inv SI (sll SI 1 crbd))))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x2f6 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x56 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x1d6 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x36 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x116 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0xf6 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x3f6 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x1eb | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set rd (div SI ra rb)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x1cb | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set rd (udiv SI ra rb)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x136 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x1b6 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | 0x0 | 0x0 | 0x0 | 0x356 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x11c | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (inv SI (xor SI rs rb))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | 0x0 | 0x0 | 0x3ba | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (ext SI (trunc QI rs))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | 0x0 | 0x0 | 0x39a | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (ext SI (trunc HI rs))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | ra | rb | 0x0 | 0x3d6 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x13 | 0x0 | 0x0 | 0x0 | 0x0 | 0x96 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x22 | rd | ra | d |
(sequence () (set rd (zext SI (mem QI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x23 | rd | ra | d |
(sequence () (set rd (zext SI (mem QI (add SI ra d)))) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x77 | 0x0 |
(sequence () (set rd (zext SI (mem QI (add SI ra rb)))) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x57 | 0x0 |
(sequence () (set rd (zext SI (mem QI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x2a | rd | ra | d |
(sequence () (set rd (ext SI (mem HI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x2b | rd | ra | d |
(sequence () (set rd (ext SI (mem HI (add SI ra d)))) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x177 | 0x0 |
(sequence () (set rd (ext SI (mem HI (add SI ra rb)))) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x157 | 0x0 |
(sequence () (set rd (ext SI (mem HI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x316 | 0x0 |
(set rd (mem HI (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x28 | rd | ra | d |
(sequence () (set rd (zext SI (mem HI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x29 | rd | ra | d |
(sequence () (set rd (zext SI (mem HI (add SI ra d)))) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x137 | 0x0 |
(sequence () (set rd (zext SI (mem HI (add SI ra rb)))) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x117 | 0x0 |
(sequence () (set rd (zext SI (mem HI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x2e | rd | ra | d |
(sequence ((AI ea) (SI n)) (set ea (add SI ra d)) (set n (index-of rd)) (if (ne 0 (and USI ea (sub INT 4 1))) (set pc (c-call IAI "@cpu@_trap" pc 1))) (if (ge n 0) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 1) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 2) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 3) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 4) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 5) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 6) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 7) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 8) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 9) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 10) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 11) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 12) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 13) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 14) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 15) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 16) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 17) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 18) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 19) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 20) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 21) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 22) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 23) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 24) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 25) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 26) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 27) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 28) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 29) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 30) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 31) (sequence () (set (reg SI h-gpr n) (mem WI ea)) (set ea (add USI ea 4)) (set n (add SI n 1)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x14 | 0x0 |
(set rd (mem WI (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x216 | 0x0 |
(set rd (mem WI (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x20 | rd | ra | d |
(sequence () (set rd (zext SI (mem SI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-d |
0x21 | rd | ra | d |
(sequence () (set rd (zext SI (mem SI (add SI ra d)))) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x37 | 0x0 |
(sequence () (set rd (zext SI (mem SI (add SI ra rb)))) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x17 | 0x0 |
(sequence () (set rd (zext SI (mem SI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)))))
0 1 2 3 4 5 | 6 7 8 | 9 10 11 | 12 13 | 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crfd | f-crfs | f-res/9-2 | f-res/14-2 | f-rb | f-oe | f-xo | f-rc |
0x13 | crfd | crfs | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 | 0x0 |
(set crfd crfs)
0 1 2 3 4 5 | 6 7 8 | 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-crfd | f-res/9-2 | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | crfd | 0x0 | 0x0 | 0x0 | 0x0 | 0x200 | 0x0 |
(set crfd (and SI (reg SI h-spr 1) 15))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | 0x0 | 0x0 | 0x0 | 0x13 | 0x0 |
(set rd (reg SI h-cr))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | 0x0 | 0x0 | 0x0 | 0x53 | 0x0 |
(set rd (reg SI h-msr))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-spr | f-oe | f-xo | f-rc |
0x1f | rd | spr | 0x0 | 0x153 | 0x0 |
(set rd spr)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 | 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-res/11-1 | f-sr | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | 0x0 | sr | 0x0 | 0x0 | 0x253 | 0x0 |
(set rd sr)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-tbr | f-oe | f-xo | f-rc |
0x1f | rd | tbr | 0x0 | 0x173 | 0x0 |
(set rd tbr)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | 0x0 | 0x0 | 0x0 | 0x92 | 0x0 |
(set (reg SI h-msr) rd)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-spr | f-oe | f-xo | f-rc |
0x1f | rs | spr | 0x0 | 0x1d3 | 0x0 |
(set spr rs)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 | 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-res/11-1 | f-sr | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | 0x0 | sr | 0x0 | 0x0 | 0xd2 | 0x0 |
(set sr rs)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0x4b | rc |
(sequence () (sequence ((DI res)) (set res (mul DI (ext DI ra) (ext DI rb))) (set rd (trunc SI (srl DI res 32)))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | 0x0 | 0xb | rc |
(sequence () (sequence ((DI res)) (set res (mul DI (zext DI ra) (zext DI rb))) (set rd (trunc SI (srl DI res 32)))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-simm |
0x7 | rd | ra | simm |
(sequence () (sequence () (set rd (mul SI ra simm))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0xeb | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set rd (mul SI ra rb))) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x1dc | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (inv SI (and SI rs rb))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | 0x0 | oe | 0x68 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set alu-ov (add-oflag SI (inv SI ra) 1 0)) (set alu-ca (add-cflag SI (inv SI ra) 1 0)) (set rd (addc SI (inv SI ra) 1 0))) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x7c | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (inv SI (or SI rs rb))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x1bc | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (or SI rs rb)) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x19c | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (or SI rs (inv SI rb))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-uimm |
0x18 | rs | ra | uimm |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (or SI rs uimm)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-uimm |
0x19 | rs | ra | uimm |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (or SI rs (sll UINT uimm 16))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x13 | 0x0 | 0x0 | 0x0 | 0x0 | 0x32 | 0x0 |
(set pc (c-call IAI "@cpu@_rfi"))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 22 23 24 25 | 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-sh | f-mb | f-me | f-rc |
0x14 | rs | ra | sh | mb | me | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence ((WI m) (WI r)) (set r (rol SI rs sh)) (set m (c-raw-call WI "MASK" (add UINT mb 32) (add UINT me 32))) (set ra (or SI (and SI r m) (and SI rs (inv SI m))))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 22 23 24 25 | 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-sh | f-mb | f-me | f-rc |
0x15 | rs | ra | sh | mb | me | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence ((WI m) (WI r)) (set r (rol SI rs sh)) (set m (c-raw-call WI "MASK" (add UINT mb 32) (add UINT me 32))) (set ra (and SI r m))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 22 23 24 25 | 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-mb | f-me | f-rc |
0x17 | rs | ra | rb | mb | me | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence ((WI m) (WI r)) (set r (rol SI rs (and SI rb 31))) (set m (c-raw-call WI "MASK" (add UINT mb 32) (add UINT me 32))) (set ra (and SI r m))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x11 | 0x0 | 0x0 | 0x0 | 0x0 | 0x1 | 0x0 |
(set pc (c-call IAI "@cpu@_trap" pc 12))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x18 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (sll SI rs (and SI rb 63))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x318 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (sra SI rs (and SI rb 63))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-sh | f-oe | f-xo | f-rc |
0x1f | rs | ra | sh | 0x0 | 0x338 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (sra SI rs sh)) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-sh | f-oe | f-xo | f-rc |
0x1f | rs | ra | sh | 0x0 | 0x218 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (srl SI rs sh)) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x26 | rs | ra | d |
(sequence () (set (mem QI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)) rs))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x27 | rs | ra | d |
(sequence () (set (mem QI (add SI ra d)) rs) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0xf7 | 0x0 |
(sequence () (set (mem QI (add SI ra rb)) rs) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0xd7 | 0x0 |
(sequence () (set (mem QI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)) rs))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x2c | rs | ra | d |
(sequence () (set (mem HI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)) rs))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x2d | rs | ra | d |
(sequence () (set (mem HI (add SI ra d)) rs) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x1b7 | 0x0 |
(sequence () (set (mem HI (add SI ra rb)) rs) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x197 | 0x0 |
(sequence () (set (mem HI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)) rs))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x2f | rs | ra | d |
(sequence ((AI ea) (SI n)) (set ea (add SI ra d)) (set n (index-of rs)) (if (ne 0 (and USI ea (sub INT 4 1))) (set pc (c-call IAI "@cpu@_trap" pc 1))) (if (ge n 0) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 1) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 2) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 3) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 4) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 5) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 6) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 7) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 8) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 9) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 10) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 11) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 12) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 13) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 14) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 15) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 16) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 17) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 18) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 19) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 20) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 21) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 22) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 23) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 24) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 25) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 26) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 27) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 28) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 29) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 30) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))) (if (ge n 31) (sequence () (set (mem WI ea) (reg SI h-gpr n)) (set ea (add USI ea 4)) (set n (add SI n 1)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x24 | rs | ra | d |
(sequence () (set (mem WI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) d)) rs))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-d |
0x25 | rs | ra | d |
(sequence () (set (mem WI (add SI ra d)) rs) (set ra (add SI ra d)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0xb7 | 0x0 |
(sequence () (set (mem WI (add SI ra rb)) rs) (set ra (add SI ra rb)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x97 | 0x0 |
(sequence () (set (mem WI (add WI (c-call WI "@cpu@_get_reg_or_zero" (index-of ra)) rb)) rs))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x28 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (set alu-ov (add-oflag SI (inv SI ra) rb 1)) (set alu-ca (add-cflag SI (inv SI ra) rb 1)) (set rd (addc SI (inv SI ra) rb 1))) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x8 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI (inv SI ra) rb 1)) (set alu-ca (add-cflag SI (inv SI ra) rb 1)) (set rd (addc SI (inv SI ra) rb 1))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | rb | oe | 0x88 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI (inv SI ra) rb xer-ca)) (set alu-ca (add-cflag SI (inv SI ra) rb xer-ca)) (set rd (addc SI (inv SI ra) rb xer-ca))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rd | f-ra | f-simm |
0x8 | rd | ra | simm |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI (inv SI ra) (add INT simm 1) 0)) (set alu-ca (add-cflag SI (inv SI ra) (add INT simm 1) 0)) (set rd (addc SI (inv SI ra) (add INT simm 1) 0))) (set-quiet xer-ca alu-ca)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | 0x0 | oe | 0xe8 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI (inv SI ra) -1 xer-ca)) (set alu-ca (add-cflag SI (inv SI ra) -1 xer-ca)) (set rd (addc SI (inv SI ra) -1 xer-ca))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rd | ra | 0x0 | oe | 0xc8 | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (sequence () (sequence () (set alu-ov (add-oflag SI (inv SI ra) 0 xer-ca)) (set alu-ca (add-cflag SI (inv SI ra) 0 xer-ca)) (set rd (addc SI (inv SI ra) 0 xer-ca))) (set-quiet xer-ca alu-ca)) (if oe (sequence () (if (eq alu-ov 1) (if (eq xer-so 0) (set-quiet xer-so alu-ov))) (set-quiet xer-ov alu-ov))) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI rd) 0) (set value (or QI value 8))) (if (gt (ext SI rd) 0) (set value (or QI value 4))) (if (eq (ext SI rd) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | 0x0 | 0x0 | 0x0 | 0x256 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | 0x0 | 0x0 | 0x0 | 0x172 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | 0x0 | rb | 0x0 | 0x132 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rd | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | 0x0 | 0x0 | 0x0 | 0x0 | 0x236 | 0x0 |
(nop)
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-to | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | to | ra | rb | 0x0 | 0x4 | 0x0 |
(sequence () (if (lt ra rb) (if (and UINT (srl UINT to 0) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (gt ra rb) (if (and UINT (srl UINT to 1) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (eq ra rb) (if (and UINT (srl UINT to 2) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (ltu ra rb) (if (and UINT (srl UINT to 3) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (gtu ra rb) (if (and UINT (srl UINT to 4) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-to | f-ra | f-simm |
0x3 | to | ra | simm |
(sequence () (if (lt ra simm) (if (and UINT (srl UINT to 0) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (gt ra simm) (if (and UINT (srl UINT to 1) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (eq ra simm) (if (and UINT (srl UINT to 2) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (ltu ra simm) (if (and UINT (srl UINT to 3) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))) (if (gtu ra simm) (if (and UINT (srl UINT to 4) 1) (set pc (c-call IAI "@cpu@_trap" pc 7)))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 | 21 | 22 23 24 25 26 27 28 29 30 | 31 |
f-opcd | f-rs | f-ra | f-rb | f-oe | f-xo | f-rc |
0x1f | rs | ra | rb | 0x0 | 0x13c | rc |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (xor SI rs rb)) (if rc (sequence ((QI value)) (set-quiet value 0) (if (lt (ext SI ra) 0) (set value (or QI value 8))) (if (gt (ext SI ra) 0) (set value (or QI value 4))) (if (eq (ext SI ra) 0) (set value (or QI value 2))) (set (reg QI h-cr/s 0) value))))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-uimm |
0x1a | rs | ra | uimm |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (xor SI rs uimm)))
0 1 2 3 4 5 | 6 7 8 9 10 | 11 12 13 14 15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
f-opcd | f-rs | f-ra | f-uimm |
0x1b | rs | ra | uimm |
(sequence ((BI alu-ov) (BI alu-ca)) (set ra (xor SI rs (sll UINT uimm 16))))
((emit addi rd ra simm))
((emit addi rd (ra 0) simm))
((emit addi rd ra simm))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/