| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0x9 | rn | rd | 0x0 |
(set rd (add DI rm rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0xc |
(set rn (add SI rn rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0xe |
(sequence ((BI flag)) (set flag (add-cflag SI rn rm tbit)) (set rn (addc SI rn rm tbit)) (set tbit flag))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x34 | rm | disp10 | rd | 0x0 |
(set rd (add DI rm (ext DI disp10)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-imm8 |
| 0x7 | rn | imm8 |
(set rn (add SI rn (ext SI (and QI imm8 255))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x35 | rm | disp10 | rd | 0x0 |
(set rd
(ext DI
(add SI (ext SI disp10) (subword SI rm 1))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0x8 | rn | rd | 0x0 |
(set rd
(add SI (subword SI rm 1) (subword SI rn 1)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0xf |
(sequence ((BI t)) (set t (add-oflag SI rn rm 0)) (set rn (add SI rn rm)) (set tbit t))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0xc | rn | rd | 0x0 |
(set rd
(zext DI
(add SI (subword SI rm 1) (subword SI rn 1))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6x32 | f-dest | f-rsvd |
| 0x38 | rm | 0x4 | disp6x32 | 0x3f | 0x0 |
(sequence () (set rm rm))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0xb | rn | rd | 0x0 |
(set rd (and DI rm rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn64 | rm64 | 0x9 |
(set rn64 (and DI rm64 rn64))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xcd | imm8 |
(sequence ((DI addr) (UQI data)) (set addr (add SI r0 gbr)) (set data (and UQI (mem UQI addr) imm8)) (set (mem UQI addr) data))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0xf | rn | rd | 0x0 |
(set rd (and DI rm (inv DI rn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x36 | rm | disp10 | rd | 0x0 |
(set rd (and DI rm (ext DI disp10)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xc9 | uimm8 |
(set r0 (and SI r0 (zext DI uimm8)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x19 | rm | 0x1 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (eq rm rn) (set pc tra)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-imm6 | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x39 | rm | 0x1 | imm6 | likely | 0x0 | tra | 0x0 |
(sequence () (if (eq rm (ext DI imm6)) (set pc tra)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-disp8 |
| 0x8b | disp8 |
(if (not BI tbit) (set pc disp8))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-disp8 |
| 0x8f | disp8 |
(if (not BI tbit)
(sequence
()
(set pc (add UDI pc 2))
(delay VOID 1 (set pc disp8))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x19 | rm | 0x3 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (ge rm rn) (set pc tra)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x19 | rm | 0xb | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (geu rm rn) (set pc tra)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x19 | rm | 0x7 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (gt rm rn) (set pc tra)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x19 | rm | 0xf | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (gtu rm rn) (set pc tra)))
| 0 1 2 3 4 5 | 6 7 8 | 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-6-3 | f-trb | f-ext | f-right | f-dest | f-rsvd |
| 0x11 | 0x0 | trb | 0x1 | 0x3f | rd | 0x0 |
(sequence () (set rd (or UDI (add UDI pc 4) 1)) (set pc trb) (if (eq (index-of rd) 63) (nop) (nop)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x19 | rm | 0x5 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (ne rm rn) (set pc tra)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x39 | rm | 0x5 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (if (ne rm (ext DI imm6)) (set pc tra)))
| 0 1 2 3 | 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op4 | f-disp12 |
| 0xa | disp12 |
(sequence () (set pc (add UDI pc 2)) (delay VOID 1 (set pc disp12)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x23 |
(sequence
()
(set pc (add UDI pc 2))
(delay VOID
1
(set pc (add DI (ext DI rn) (add UDI pc 4)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | 0x3f | 0x5 | 0x3f | 0x3f | 0x0 |
(c-call VOID "sh64_break" pc)
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x3b |
(c-call VOID "sh64_break" pc)
| 0 1 2 3 | 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op4 | f-disp12 |
| 0xb | disp12 |
(sequence () (delay VOID 1 (set pr (add UDI pc 4))) (set pc (add UDI pc 2)) (delay VOID 1 (set pc disp12)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x3 |
(sequence
()
(delay VOID 1 (set pr (add UDI pc 4)))
(set pc (add UDI pc 2))
(delay VOID
1
(set pc (add DI (ext DI rn) (add UDI pc 4)))))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-disp8 |
| 0x89 | disp8 |
(if tbit (set pc disp8))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-disp8 |
| 0x8d | disp8 |
(if tbit
(sequence
()
(set pc (add UDI pc 2))
(delay VOID 1 (set pc disp8))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0xf | 0x3f | rd | 0x0 |
(sequence
((DI source) (DI result))
(set source rm)
(set result 0)
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(sequence
()
(set result
(or DI (sll DI result 8) (and DI source 255)))
(set source (srl DI source 8)))
(set rd result))
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x28 |
(sequence () (set macl 0) (set mach 0))
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x48 |
(set sbit 0)
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x8 |
(set tbit 0)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0x1 | rn | rd | 0x0 |
(set rd (if DI (eq rm rn) 1 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x0 |
(set tbit (eq rm rn))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0x88 | imm8 |
(set tbit (eq r0 (ext SI (and QI imm8 255))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x3 |
(set tbit (ge rn rm))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0x3 | rn | rd | 0x0 |
(set rd (if DI (gt rm rn) 1 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x7 |
(set tbit (gt rn rm))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0x7 | rn | rd | 0x0 |
(set rd (if DI (gtu rm rn) 1 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x6 |
(set tbit (gtu rn rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x2 |
(set tbit (geu rn rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x15 |
(set tbit (gt rn 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x11 |
(set tbit (ge rn 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0xc |
(sequence ((BI t) (SI temp)) (set temp (xor SI rm rn)) (set t (eq (and SI temp 4278190080) 0)) (set t (or BI (eq (and SI temp 16711680) 0) t)) (set t (or BI (eq (and SI temp 65280) 0) t)) (set t (or BI (eq (and SI temp 255) 0) t)) (set tbit (if BI (gtu t 0) 1 0)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x8 | rm | 0x1 | rn | rd | 0x0 |
(if (eq rm 0) (set rd rn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x8 | rm | 0x5 | rn | rd | 0x0 |
(if (ne rm 0) (set rd rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x7 |
(sequence
()
(set qbit (srl SI rn 31))
(set mbit (srl SI rm 31))
(set tbit
(if BI (eq (srl SI rm 31) (srl SI rn 31)) 0 1)))
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x19 |
(sequence () (set tbit 0) (set qbit 0) (set mbit 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x4 |
(sequence
((BI oldq) (SI tmp0) (UQI tmp1))
(set oldq qbit)
(set qbit (srl SI rn 31))
(set rn (or SI (sll SI rn 1) (zext SI tbit)))
(if (not BI oldq)
(if (not BI mbit)
(sequence
()
(set tmp0 rn)
(set rn (sub SI rn rm))
(set tmp1 (gtu rn tmp0))
(if (not BI qbit)
(set qbit (if BI tmp1 1 0))
(set qbit (if BI (eq tmp1 0) 1 0))))
(sequence
()
(set tmp0 rn)
(set rn (add SI rn rm))
(set tmp1 (ltu rn tmp0))
(if (not BI qbit)
(set qbit (if BI (eq tmp1 0) 1 0))
(set qbit (if BI tmp1 1 0)))))
(if (not BI mbit)
(sequence
()
(set tmp0 rn)
(set rn (add SI rm rn))
(set tmp1 (ltu rn tmp0))
(if (not BI qbit)
(set qbit (if BI tmp1 1 0))
(set qbit (if BI (eq tmp1 0) 1 0))))
(sequence
()
(set tmp0 rn)
(set rn (sub SI rn rm))
(set tmp1 (gtu rn tmp0))
(if (not BI qbit)
(set qbit (if BI (eq tmp1 0) 1 0))
(set qbit (if BI tmp1 1 0))))))
(set tbit (if BI (eq qbit mbit) 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x84 |
(set rn (udiv SI rn r0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0xd |
(sequence ((DI result)) (set result (mul DI (ext DI rm) (ext DI rn))) (set mach (subword SI result 0)) (set macl (subword SI result 1)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x5 |
(sequence ((DI result)) (set result (mul DI (zext DI rm) (zext DI rn))) (set mach (subword SI result 0)) (set macl (subword SI result 1)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x10 |
(sequence () (set rn (sub SI rn 1)) (set tbit (eq rn 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0xe |
(set rn (ext SI (subword QI rm 3)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0xf |
(set rn (ext SI (subword HI rm 1)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0xc |
(set rn (zext SI (subword QI rm 3)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0xd |
(set rn (zext SI (subword HI rm 1)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | fsdn | 0x5d |
(if prbit
(set fsdn (c-call DF "sh64_fabsd" fsdn))
(set fsdn (c-call SF "sh64_fabss" fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0x6 | drgh | 0x1 | drf | 0x0 |
(set drf (c-call DF "sh64_fabsd" drgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0x6 | frgh | 0x0 | frf | 0x0 |
(set frf (c-call SF "sh64_fabss" frgh))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fsdn | fsdm | 0x0 |
(if prbit
(set fsdn (c-call DF "sh64_faddd" fsdm fsdn))
(set fsdn (c-call SF "sh64_fadds" fsdm fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | drg | 0x1 | drh | drf | 0x0 |
(set drf (c-call DF "sh64_faddd" drg drh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | frg | 0x0 | frh | frf | 0x0 |
(set frf (c-call SF "sh64_fadds" frg frh))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fsdn | fsdm | 0x4 |
(if prbit
(set tbit (c-call BI "sh64_fcmpeqd" fsdm fsdn))
(set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | drg | 0x9 | drh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpeqd" drg drh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | frg | 0x8 | frh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpeqs" frg frh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | drg | 0xf | drh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpged" drg drh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | frg | 0xe | frh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpges" frg frh)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fsdn | fsdm | 0x5 |
(if prbit
(set tbit (c-call BI "sh64_fcmpgtd" fsdn fsdm))
(set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | drg | 0xd | drh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpgtd" drg drh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | frg | 0xc | frh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpgts" frg frh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | drg | 0xb | drh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpund" drg drh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xc | frg | 0xa | frh | rd | 0x0 |
(set rd
(zext DI (c-call BI "sh64_fcmpuns" frg frh)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0x7 | frf | 0x0 |
(set frf (c-call SF "sh64_fcnvds" drgh))
| 0 1 2 3 | 4 5 6 | 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-dn | f-7-1 | f-sub8 |
| 0xf | drn | 0x0 | 0xbd |
(set fpul (c-call SF "sh64_fcnvds" drn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0x6 | drf | 0x0 |
(set drf (c-call DF "sh64_fcnvsd" frgh))
| 0 1 2 3 | 4 5 6 | 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-dn | f-7-1 | f-sub8 |
| 0xf | drn | 0x0 | 0xad |
(set drn (c-call DF "sh64_fcnvsd" fpul))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fsdn | fsdm | 0x3 |
(if prbit
(set fsdn (c-call DF "sh64_fdivd" fsdn fsdm))
(set fsdn (c-call SF "sh64_fdivs" fsdn fsdm)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | drg | 0x5 | drh | drf | 0x0 |
(set drf (c-call DF "sh64_fdivd" drg drh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | frg | 0x4 | frh | frf | 0x0 |
(set frf (c-call SF "sh64_fdivs" frg frh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x7 | 0x3f | 0x2 | 0x3f | frf | 0x0 |
(set frf (subword SF fpscr 0))
| 0 1 2 3 | 4 5 | 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-vn | f-vm | f-sub8 |
| 0xf | fvn | fvm | 0xed |
(c-call VOID "sh64_fipr" (index-of fvm) (index-of fvn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x5 | fvg | 0x6 | fvh | frf | 0x0 |
(sequence
()
(set fvg fvg)
(set fvh fvh)
(set frf
(c-call
SF
"sh64_fiprs"
(index-of fvg)
(index-of fvh))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x8 | f-dest | f-rsvd |
| 0x27 | rm | disp10x8 | drf | 0x0 |
(set drf (mem DF (add DI rm disp10x8)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | frn | 0x8d |
(set frn (c-call SF "sh64_fldi0"))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | frn | 0x9d |
(set frn (c-call SF "sh64_fldi1"))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x8 | f-dest | f-rsvd |
| 0x26 | rm | disp10x8 | fpf | 0x0 |
(sequence
()
(set fpf fpf)
(c-call
VOID
"sh64_fldp"
pc
rm
disp10x8
(index-of fpf)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x4 | f-dest | f-rsvd |
| 0x25 | rm | disp10x4 | frf | 0x0 |
(set frf (mem SF (add DI rm disp10x4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | frn | 0x1d |
(set fpul frn)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x7 | rm | 0x9 | rn | frf | 0x0 |
(set drf (mem DF (add DI rm rn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x7 | rm | 0xd | rn | fpf | 0x0 |
(sequence () (set fpf fpf) (c-call VOID "sh64_fldp" pc rm rn (index-of fpf)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x7 | rm | 0x8 | rn | frf | 0x0 |
(set frf (mem SF (add DI rm rn)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | fsdn | 0x2d |
(if prbit
(set fsdn (c-call DF "sh64_floatld" fpul))
(set fsdn (c-call SF "sh64_floatls" fpul)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0xe | drf | 0x0 |
(set drf (c-call DF "sh64_floatld" frgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0xc | frf | 0x0 |
(set frf (c-call SF "sh64_floatls" frgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0xd | drf | 0x0 |
(set drf (c-call DF "sh64_floatqd" drgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0xf | frf | 0x0 |
(set frf (c-call SF "sh64_floatqs" drgh))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | frn | frm | 0xe |
(set frn (c-call SF "sh64_fmacs" fr0 frm frn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | frg | 0xe | frh | frf | 0x0 |
(set frf
(c-call
SF
"sh64_fadds"
frf
(c-call SF "sh64_fmuls" frg frh)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fmovn | fmovm | 0xc |
(set fmovn fmovm)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fmovn | rm | 0x8 |
(if (not BI szbit)
(set fmovn (mem SF rm))
(set fmovn (mem DF rm)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fmovn | rm | 0x9 |
(if (not BI szbit)
(sequence
()
(set fmovn (mem SF rm))
(set rm (add SI rm 4)))
(sequence
()
(set fmovn (mem DF rm))
(set rm (add SI rm 8))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fmovn | rm | 0x6 |
(if (not BI szbit)
(set fmovn (mem SF (add SI r0 rm)))
(set fmovn (mem DF (add SI r0 rm))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | rn | fmovm | 0xa |
(if (not BI szbit)
(set (mem SF rn) fmovm)
(set (mem DF rn) fmovm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | rn | fmovm | 0xb |
(if (not BI szbit)
(sequence
()
(set rn (sub SI rn 4))
(set (mem SF rn) fmovm))
(sequence
()
(set rn (sub SI rn 8))
(set (mem DF rn) fmovm)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | rn | fmovm | 0x7 |
(if (not BI szbit)
(set (mem SF (add SI r0 rn)) fmovm)
(set (mem DF (add SI r0 rn)) fmovm))
| 0 1 2 3 | 4 5 6 | 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
| f-op4 | f-dn | f-7-1 | f-rm | f-sub4 | f-16-4 | f-imm12x8 |
| 0x3 | drn | 0x0 | rm | 0x1 | 0x7 | imm12x8 |
(set drn (mem DF (add SI rm imm12x8)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 | 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
| f-op4 | f-rn | f-dm | f-11-1 | f-sub4 | f-16-4 | f-imm12x8 |
| 0x3 | rn | drm | 0x0 | 0x1 | 0x3 | imm12x8 |
(set (mem DF (add SI rn imm12x8)) drm)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0x1 | drf | 0x0 |
(set drf drgh)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xc | drgh | 0x1 | rd | 0x0 |
(set rd (subword DI drgh 0))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x7 | rm | 0x0 | 0x3f | frf | 0x0 |
(set frf (subword SF (subword SI rm 1) 0))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x7 | rm | 0x1 | 0x3f | frf | 0x0 |
(set drf (subword DF rm 0))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0x0 | frf | 0x0 |
(set frf frgh)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xc | frgh | 0x0 | rd | 0x0 |
(set rd (ext DI (subword SI frgh 1)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fsdn | fsdm | 0x2 |
(if prbit
(set fsdn (c-call DF "sh64_fmuld" fsdm fsdn))
(set fsdn (c-call SF "sh64_fmuls" fsdm fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | drg | 0x7 | drh | drf | 0x0 |
(set drf (c-call DF "sh64_fmuld" drg drh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | frg | 0x6 | frh | frf | 0x0 |
(set frf (c-call SF "sh64_fmuls" frg frh))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | fsdn | 0x4d |
(if prbit
(set fsdn (c-call DF "sh64_fnegd" fsdn))
(set fsdn (c-call SF "sh64_fnegs" fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0x6 | drgh | 0x3 | drf | 0x0 |
(set drf (c-call DF "sh64_fnegd" drgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0x6 | frgh | 0x2 | frf | 0x0 |
(set frf (c-call SF "sh64_fnegs" frgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xc | frgh | 0x2 | 0x3f | 0x0 |
(set fpscr (subword SI frgh 0))
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0xfbfd |
(set frbit (not BI frbit))
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0xf3fd |
(set szbit (not BI szbit))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | fsdn | 0x6d |
(if prbit
(set fsdn (c-call DF "sh64_fsqrtd" fsdn))
(set fsdn (c-call SF "sh64_fsqrts" fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0x5 | drf | 0x0 |
(set drf (c-call DF "sh64_fsqrtd" drgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0x4 | frf | 0x0 |
(set frf (c-call SF "sh64_fsqrts" frgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x8 | f-dest | f-rsvd |
| 0x2f | rm | disp10x8 | drf | 0x0 |
(set (mem DF (add DI rm disp10x8)) drf)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x8 | f-dest | f-rsvd |
| 0x2e | rm | disp10x8 | fpf | 0x0 |
(sequence
()
(set fpf fpf)
(c-call
VOID
"sh64_fstp"
pc
rm
disp10x8
(index-of fpf)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x4 | f-dest | f-rsvd |
| 0x2d | rm | disp10x4 | frf | 0x0 |
(set (mem SF (add DI rm disp10x4)) frf)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | frn | 0xd |
(set frn fpul)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xf | rm | 0x9 | rn | drf | 0x0 |
(set (mem DF (add DI rm rn)) drf)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xf | rm | 0xd | rn | fpf | 0x0 |
(sequence () (set fpf fpf) (c-call VOID "sh64_fstp" pc rm rn (index-of fpf)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xf | rm | 0x8 | rn | frf | 0x0 |
(set (mem SF (add DI rm rn)) frf)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0xf | fsdn | fsdm | 0x1 |
(if prbit
(set fsdn (c-call DF "sh64_fsubd" fsdn fsdm))
(set fsdn (c-call SF "sh64_fsubs" fsdn fsdm)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | frg | 0x3 | frh | frf | 0x0 |
(set drf (c-call DF "sh64_fsubd" drg drh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xd | frg | 0x2 | frh | frf | 0x0 |
(set frf (c-call SF "sh64_fsubs" frg frh))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0xf | fsdn | 0x3d |
(set fpul
(if SF
prbit
(c-call SF "sh64_ftrcdl" fsdn)
(c-call SF "sh64_ftrcsl" fsdn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0xb | frf | 0x0 |
(set frf (c-call SF "sh64_ftrcdl" drgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | drgh | 0x9 | frf | 0x0 |
(set drf (c-call DF "sh64_ftrcdq" drgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0x8 | frf | 0x0 |
(set frf (c-call SF "sh64_ftrcsl" frgh))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 | 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left-right | f-ext | f-dest | f-rsvd |
| 0xe | frgh | 0xa | drf | 0x0 |
(set drf (c-call DF "sh64_ftrcsq" frgh))
| 0 1 2 3 | 4 5 | 6 7 8 9 10 11 12 13 14 15 |
| f-op4 | f-vn | f-sub10 |
| 0xf | fvn | 0x1fd |
(c-call VOID "sh64_ftrv" (index-of fvn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x5 | mtrxg | 0xe | fvh | fvf | 0x0 |
(sequence
()
(set mtrxg mtrxg)
(set fvh fvh)
(set fvf fvf)
(c-call
VOID
"sh64_ftrvs"
(index-of mtrxg)
(index-of fvh)
(index-of fvf)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x30 | rm | 0xf | disp6 | rd | 0x0 |
(sequence ((SI address)) (set address (add DI rm disp6)) (set rd (mem SI address)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x9 | crk | 0xf | 0x3f | rd | 0x0 |
(set rd crk)
| 0 1 2 3 4 5 | 6 7 8 | 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-6-3 | f-trb | f-ext | f-right | f-dest | f-rsvd |
| 0x11 | 0x0 | trb | 0x5 | 0x3f | rd | 0x0 |
(set rd trb)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6x32 | f-dest | f-rsvd |
| 0x38 | rm | 0x5 | disp6x32 | 0x3f | 0x0 |
(sequence () (set rm rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x2b |
(sequence () (set pc (add UDI pc 2)) (delay VOID 1 (set pc rn)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0xb |
(sequence () (delay VOID 1 (set pr (add UDI pc 4))) (set pc (add UDI pc 2)) (delay VOID 1 (set pc rn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x20 | rm | disp10 | rd | 0x0 |
(set rd
(ext DI (mem QI (add DI rm (ext DI disp10)))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x1e |
(set gbr rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0xe |
(set (reg SI h-sr) rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x2e |
(set vbr rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x17 |
(sequence () (set gbr (mem SI rn)) (set rn (add SI rn 4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x27 |
(sequence () (set vbr (mem SI rn)) (set rn (add SI rn 4)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x30 | rm | 0x6 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (SI val))
(set addr (add DI rm disp6))
(set bytecount (add DI (and DI addr 3) 1))
(set val 0)
(if (and QI bytecount 4)
(set rd (ext DI (mem SI (and DI addr -4))))
(if endian
(sequence
()
(if (and QI bytecount 2)
(set val
(add SI
(sll SI val 16)
(zext DI (mem HI (and DI addr -4))))))
(if (and QI bytecount 1)
(set val
(add SI (sll SI val 8) (zext DI (mem QI addr)))))
(set rd (ext DI val)))
(sequence
()
(if (and QI bytecount 1)
(set val
(add SI (sll SI val 8) (zext DI (mem QI addr)))))
(if (and QI bytecount 2)
(set val
(add SI
(sll SI val 16)
(zext DI (mem HI (and DI addr -4))))))
(set rd
(ext DI
(sll SI val (sub INT 32 (mul INT 8 bytecount)))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x30 | rm | 0x7 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (DI val))
(set addr (add DI rm disp6))
(set bytecount (add DI (and DI addr 7) 1))
(set val 0)
(if (and QI bytecount 8)
(set rd (mem DI (and DI addr -8)))
(if endian
(sequence
()
(if (and QI bytecount 4)
(set val
(add DI
(sll DI val 32)
(zext DI (mem SI (and DI addr -8))))))
(if (and QI bytecount 2)
(set val
(add DI
(sll DI val 16)
(zext DI (mem HI (and DI addr -4))))))
(if (and QI bytecount 1)
(set val
(add DI (sll DI val 8) (zext DI (mem QI addr)))))
(set rd val))
(sequence
()
(if (and QI bytecount 1)
(set val
(add DI (sll DI val 8) (zext DI (mem QI addr)))))
(if (and QI bytecount 2)
(set val
(add DI
(sll DI val 16)
(zext DI (mem HI (and DI addr -4))))))
(if (and QI bytecount 4)
(set val
(add DI
(sll DI val 32)
(zext DI (mem SI (and DI addr -8))))))
(set rd
(sll DI val (sub INT 64 (mul INT 8 bytecount))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x4 | f-dest | f-rsvd |
| 0x22 | rm | disp10x4 | rd | 0x0 |
(set rd
(ext DI (mem SI (add DI rm (ext DI disp10x4)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x30 | rm | 0x2 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (SI val))
(set addr (add DI rm disp6))
(set bytecount (sub INT 4 (and DI addr 3)))
(set val 0)
(if (and QI bytecount 4)
(set rd (ext DI (mem SI addr)))
(if endian
(sequence
()
(if (and QI bytecount 1)
(set val
(add SI (sll SI val 8) (zext DI (mem QI addr)))))
(if (and QI bytecount 2)
(set val
(add SI
(sll SI val 16)
(zext DI (mem HI (and DI (add DI addr 1) -2))))))
(set rd
(ext DI
(sll SI val (sub INT 32 (mul INT 8 bytecount))))))
(sequence
()
(if (and QI bytecount 2)
(set val
(add SI
(sll SI val 16)
(zext DI (mem HI (and DI (add DI addr 1) -2))))))
(if (and QI bytecount 1)
(set val
(add SI (sll SI val 8) (zext DI (mem QI addr)))))
(set rd (ext DI val))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x30 | rm | 0x3 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (DI val))
(set addr (add DI rm disp6))
(set bytecount (sub INT 8 (and DI addr 7)))
(set val 0)
(if (and QI bytecount 8)
(set rd (mem DI addr))
(if endian
(sequence
()
(if (and QI bytecount 1)
(set val
(add DI (sll DI val 8) (zext DI (mem QI addr)))))
(if (and QI bytecount 2)
(set val
(add DI
(sll DI val 16)
(zext DI (mem HI (and DI (add DI addr 1) -2))))))
(if (and QI bytecount 4)
(set val
(add DI
(sll DI val 32)
(zext DI (mem SI (and DI (add DI addr 3) -4))))))
(set rd
(sll DI val (sub INT 64 (mul INT 8 bytecount)))))
(sequence
()
(if (and QI bytecount 4)
(set val
(add DI
(sll DI val 32)
(zext DI (mem SI (and DI (add DI addr 3) -4))))))
(if (and QI bytecount 2)
(set val
(add DI
(sll DI val 16)
(zext DI (mem HI (and DI (add DI addr 1) -2))))))
(if (and QI bytecount 1)
(set val
(add DI (sll DI val 8) (zext DI (mem QI addr)))))
(set rd val)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x8 | f-dest | f-rsvd |
| 0x23 | rm | disp10x8 | rd | 0x0 |
(set rd (mem DI (add DI rm (ext DI disp10x8))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x6a |
(set fpscr rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x5a |
(set fpul (subword SF rn 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0xa |
(set mach rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x1a |
(set macl rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x2a |
(set pr rn)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x66 |
(sequence () (set fpscr (mem SI rn)) (set rn (add SI rn 4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x56 |
(sequence () (set fpul (mem SF rn)) (set rn (add SI rn 4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x6 |
(sequence () (set mach (mem SI rn)) (set rn (add SI rn 4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x16 |
(sequence () (set macl (mem SI rn)) (set rn (add SI rn 4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x26 |
(sequence () (set pr (mem SI rn)) (set rn (add SI rn 4)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x24 | rm | disp10 | rd | 0x0 |
(set rd
(zext DI (mem QI (add DI rm (ext DI disp10)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x2c | rm | disp10 | rd | 0x0 |
(set rd
(zext DI (mem HI (add DI rm (ext DI disp10x2)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x21 | rm | disp10 | rd | 0x0 |
(set rd
(ext DI (mem HI (add DI rm (ext DI disp10x2)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x10 | rm | 0x0 | rn | rd | 0x0 |
(set rd (ext DI (mem QI (add DI rm rn))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x10 | rm | 0x2 | rn | rd | 0x0 |
(set rd (ext DI (mem SI (add DI rm rn))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x10 | rm | 0x3 | rn | rd | 0x0 |
(set rd (mem DI (add DI rm rn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x10 | rm | 0x4 | rn | rd | 0x0 |
(set rd (zext DI (mem UQI (add DI rm rn))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x10 | rm | 0x5 | rn | rd | 0x0 |
(set rd (zext DI (mem UHI (add DI rm rn))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x10 | rm | 0x1 | rn | rd | 0x0 |
(set rd (ext DI (mem HI (add DI rm rn))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0xa | 0x3f | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0 (abs SI (subword SI rm 1)))
(set result1 (abs SI (subword SI rm 0)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x9 | 0x3f | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0 (abs HI (subword HI rm 3)))
(set result1 (abs HI (subword HI rm 2)))
(set result2 (abs HI (subword HI rm 1)))
(set result3 (abs HI (subword HI rm 0)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0xf |
(sequence
((DI tmpry) (DI mac) (DI result) (SI x) (SI y))
(set x (mem SI rn))
(set rn (add SI rn 4))
(if (eq (index-of rn) (index-of rm))
(sequence
()
(set rn (add SI rn 4))
(set rm (add SI rm 4))))
(set y (mem SI rm))
(set rm (add SI rm 4))
(set tmpry (mul DI (zext DI x) (zext DI y)))
(set mac
(or DI (sll DI (zext DI mach) 32) (zext DI macl)))
(set result (add DI mac tmpry))
(sequence
()
(if sbit
(sequence
((SI min) (SI max))
(set max (srl DI (inv DI 0) 16))
(set min (srl DI (inv DI 0) 15))
(if (gt result max)
(set result max)
(if (lt result min) (set result min)))))
(set mach (subword SI result 0))
(set macl (subword SI result 1))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x4 | rn | rm | 0xf |
(sequence
((SI tmpry) (DI mac) (DI result) (HI x) (HI y))
(set x (mem HI rn))
(set rn (add SI rn 2))
(if (eq (index-of rn) (index-of rm))
(sequence
()
(set rn (add SI rn 2))
(set rm (add SI rm 2))))
(set y (mem HI rm))
(set rm (add SI rm 2))
(set tmpry (mul SI (zext SI x) (zext SI y)))
(if sbit
(sequence
()
(if (add-oflag SI tmpry macl 0) (set mach 1))
(set macl (add SI tmpry macl)))
(sequence
()
(set mac
(or DI (sll DI (zext DI mach) 32) (zext DI macl)))
(set result (add DI mac (ext DI tmpry)))
(set mach (subword SI result 0))
(set macl (subword SI result 1)))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0x2 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(add SI (subword SI rm 1) (subword SI rn 1)))
(set result1
(add SI (subword SI rm 0) (subword SI rn 0)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0x6 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(if SI
(lt (add DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1)))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (add DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1)))
(sll DI 1 (sub INT 32 1)))
(add DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1)))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result1
(if SI
(lt (add DI
(ext DI (subword SI rm 0))
(ext DI (subword SI rn 0)))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (add DI
(ext DI (subword SI rm 0))
(ext DI (subword SI rn 0)))
(sll DI 1 (sub INT 32 1)))
(add DI
(ext DI (subword SI rm 0))
(ext DI (subword SI rn 0)))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0x4 | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if QI
(lt (add DI
(zext DI (subword QI rm 7))
(zext DI (subword QI rn 7)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 7))
(zext DI (subword QI rn 7)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 7))
(zext DI (subword QI rn 7)))
(sub QI (sll QI 1 8) 1))))
(set result1
(if QI
(lt (add DI
(zext DI (subword QI rm 6))
(zext DI (subword QI rn 6)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 6))
(zext DI (subword QI rn 6)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 6))
(zext DI (subword QI rn 6)))
(sub QI (sll QI 1 8) 1))))
(set result2
(if QI
(lt (add DI
(zext DI (subword QI rm 5))
(zext DI (subword QI rn 5)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 5))
(zext DI (subword QI rn 5)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 5))
(zext DI (subword QI rn 5)))
(sub QI (sll QI 1 8) 1))))
(set result3
(if QI
(lt (add DI
(zext DI (subword QI rm 4))
(zext DI (subword QI rn 4)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 4))
(zext DI (subword QI rn 4)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 4))
(zext DI (subword QI rn 4)))
(sub QI (sll QI 1 8) 1))))
(set result4
(if QI
(lt (add DI
(zext DI (subword QI rm 3))
(zext DI (subword QI rn 3)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 3))
(zext DI (subword QI rn 3)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 3))
(zext DI (subword QI rn 3)))
(sub QI (sll QI 1 8) 1))))
(set result5
(if QI
(lt (add DI
(zext DI (subword QI rm 2))
(zext DI (subword QI rn 2)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 2))
(zext DI (subword QI rn 2)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 2))
(zext DI (subword QI rn 2)))
(sub QI (sll QI 1 8) 1))))
(set result6
(if QI
(lt (add DI
(zext DI (subword QI rm 1))
(zext DI (subword QI rn 1)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 1))
(zext DI (subword QI rn 1)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 1))
(zext DI (subword QI rn 1)))
(sub QI (sll QI 1 8) 1))))
(set result7
(if QI
(lt (add DI
(zext DI (subword QI rm 0))
(zext DI (subword QI rn 0)))
0)
0
(if QI
(lt (add DI
(zext DI (subword QI rm 0))
(zext DI (subword QI rn 0)))
(sll DI 1 8))
(add DI
(zext DI (subword QI rm 0))
(zext DI (subword QI rn 0)))
(sub QI (sll QI 1 8) 1))))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0x5 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(if HI
(lt (add DI
(ext DI (subword HI rm 3))
(ext DI (subword HI rn 3)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (add DI
(ext DI (subword HI rm 3))
(ext DI (subword HI rn 3)))
(sll DI 1 (sub INT 16 1)))
(add DI
(ext DI (subword HI rm 3))
(ext DI (subword HI rn 3)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result1
(if HI
(lt (add DI
(ext DI (subword HI rm 2))
(ext DI (subword HI rn 2)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (add DI
(ext DI (subword HI rm 2))
(ext DI (subword HI rn 2)))
(sll DI 1 (sub INT 16 1)))
(add DI
(ext DI (subword HI rm 2))
(ext DI (subword HI rn 2)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result2
(if HI
(lt (add DI
(ext DI (subword HI rm 1))
(ext DI (subword HI rn 1)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (add DI
(ext DI (subword HI rm 1))
(ext DI (subword HI rn 1)))
(sll DI 1 (sub INT 16 1)))
(add DI
(ext DI (subword HI rm 1))
(ext DI (subword HI rn 1)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result3
(if HI
(lt (add DI
(ext DI (subword HI rm 0))
(ext DI (subword HI rn 0)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (add DI
(ext DI (subword HI rm 0))
(ext DI (subword HI rn 0)))
(sll DI 1 (sub INT 16 1)))
(add DI
(ext DI (subword HI rm 0))
(ext DI (subword HI rn 0)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0x1 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(add HI (subword HI rm 3) (subword HI rn 3)))
(set result1
(add HI (subword HI rm 2) (subword HI rn 2)))
(set result2
(add HI (subword HI rm 1) (subword HI rn 1)))
(set result3
(add HI (subword HI rm 0) (subword HI rn 0)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x0 | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if QI
(eq (subword QI rm 7) (subword QI rn 7))
(inv QI 0)
0))
(set result1
(if QI
(eq (subword QI rm 6) (subword QI rn 6))
(inv QI 0)
0))
(set result2
(if QI
(eq (subword QI rm 5) (subword QI rn 5))
(inv QI 0)
0))
(set result3
(if QI
(eq (subword QI rm 4) (subword QI rn 4))
(inv QI 0)
0))
(set result4
(if QI
(eq (subword QI rm 3) (subword QI rn 3))
(inv QI 0)
0))
(set result5
(if QI
(eq (subword QI rm 2) (subword QI rn 2))
(inv QI 0)
0))
(set result6
(if QI
(eq (subword QI rm 1) (subword QI rn 1))
(inv QI 0)
0))
(set result7
(if QI
(eq (subword QI rm 0) (subword QI rn 0))
(inv QI 0)
0))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x2 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(if SI
(eq (subword SI rm 1) (subword SI rn 1))
(inv SI 0)
0))
(set result1
(if SI
(eq (subword SI rm 0) (subword SI rn 0))
(inv SI 0)
0))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x1 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(if HI
(eq (subword HI rm 3) (subword HI rn 3))
(inv HI 0)
0))
(set result1
(if HI
(eq (subword HI rm 2) (subword HI rn 2))
(inv HI 0)
0))
(set result2
(if HI
(eq (subword HI rm 1) (subword HI rn 1))
(inv HI 0)
0))
(set result3
(if HI
(eq (subword HI rm 0) (subword HI rn 0))
(inv HI 0)
0))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x6 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(if SI
(gt (subword SI rm 1) (subword SI rn 1))
(inv SI 0)
0))
(set result1
(if SI
(gt (subword SI rm 0) (subword SI rn 0))
(inv SI 0)
0))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x4 | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if QI
(gtu (subword QI rm 7) (subword QI rn 7))
(inv QI 0)
0))
(set result1
(if QI
(gtu (subword QI rm 6) (subword QI rn 6))
(inv QI 0)
0))
(set result2
(if QI
(gtu (subword QI rm 5) (subword QI rn 5))
(inv QI 0)
0))
(set result3
(if QI
(gtu (subword QI rm 4) (subword QI rn 4))
(inv QI 0)
0))
(set result4
(if QI
(gtu (subword QI rm 3) (subword QI rn 3))
(inv QI 0)
0))
(set result5
(if QI
(gtu (subword QI rm 2) (subword QI rn 2))
(inv QI 0)
0))
(set result6
(if QI
(gtu (subword QI rm 1) (subword QI rn 1))
(inv QI 0)
0))
(set result7
(if QI
(gtu (subword QI rm 0) (subword QI rn 0))
(inv QI 0)
0))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x5 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(if HI
(gt (subword HI rm 3) (subword HI rn 3))
(inv HI 0)
0))
(set result1
(if HI
(gt (subword HI rm 2) (subword HI rn 2))
(inv HI 0)
0))
(set result2
(if HI
(gt (subword HI rm 1) (subword HI rn 1))
(inv HI 0)
0))
(set result3
(if HI
(gt (subword HI rm 0) (subword HI rn 0))
(inv HI 0)
0))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x12 | rm | 0x3 | rn | rd | 0x0 |
(set rd
(or DI (and DI rm rn) (and DI rd (inv DI rn))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0xd | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(if HI
(lt (subword SI rm 1)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (subword SI rm 1) (sll DI 1 (sub INT 16 1)))
(subword SI rm 1)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result1
(if HI
(lt (subword SI rm 0)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (subword SI rm 0) (sll DI 1 (sub INT 16 1)))
(subword SI rm 0)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result2
(if HI
(lt (subword SI rn 1)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (subword SI rn 1) (sll DI 1 (sub INT 16 1)))
(subword SI rn 1)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result3
(if HI
(lt (subword SI rn 0)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (subword SI rn 0) (sll DI 1 (sub INT 16 1)))
(subword SI rn 0)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0x8 | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if QI
(lt (subword HI rm 3)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rm 3) (sll DI 1 (sub INT 8 1)))
(subword HI rm 3)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result1
(if QI
(lt (subword HI rm 2)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rm 2) (sll DI 1 (sub INT 8 1)))
(subword HI rm 2)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result2
(if QI
(lt (subword HI rm 1)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rm 1) (sll DI 1 (sub INT 8 1)))
(subword HI rm 1)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result3
(if QI
(lt (subword HI rm 0)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rm 0) (sll DI 1 (sub INT 8 1)))
(subword HI rm 0)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result4
(if QI
(lt (subword HI rn 3)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rn 3) (sll DI 1 (sub INT 8 1)))
(subword HI rn 3)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result5
(if QI
(lt (subword HI rn 2)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rn 2) (sll DI 1 (sub INT 8 1)))
(subword HI rn 2)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result6
(if QI
(lt (subword HI rn 1)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rn 1) (sll DI 1 (sub INT 8 1)))
(subword HI rn 1)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set result7
(if QI
(lt (subword HI rn 0)
(neg DI (sll DI 1 (sub INT 8 1))))
(neg QI (sll QI 1 (sub INT 8 1)))
(if QI
(lt (subword HI rn 0) (sll DI 1 (sub INT 8 1)))
(subword HI rn 0)
(sub QI (sll QI 1 (sub INT 8 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0xc | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if QI
(lt (subword HI rm 3) 0)
0
(if QI
(lt (subword HI rm 3) (sll DI 1 8))
(subword HI rm 3)
(sub QI (sll QI 1 8) 1))))
(set result1
(if QI
(lt (subword HI rm 2) 0)
0
(if QI
(lt (subword HI rm 2) (sll DI 1 8))
(subword HI rm 2)
(sub QI (sll QI 1 8) 1))))
(set result2
(if QI
(lt (subword HI rm 1) 0)
0
(if QI
(lt (subword HI rm 1) (sll DI 1 8))
(subword HI rm 1)
(sub QI (sll QI 1 8) 1))))
(set result3
(if QI
(lt (subword HI rm 0) 0)
0
(if QI
(lt (subword HI rm 0) (sll DI 1 8))
(subword HI rm 0)
(sub QI (sll QI 1 8) 1))))
(set result4
(if QI
(lt (subword HI rn 3) 0)
0
(if QI
(lt (subword HI rn 3) (sll DI 1 8))
(subword HI rn 3)
(sub QI (sll QI 1 8) 1))))
(set result5
(if QI
(lt (subword HI rn 2) 0)
0
(if QI
(lt (subword HI rn 2) (sll DI 1 8))
(subword HI rn 2)
(sub QI (sll QI 1 8) 1))))
(set result6
(if QI
(lt (subword HI rn 1) 0)
0
(if QI
(lt (subword HI rn 1) (sll DI 1 8))
(subword HI rn 1)
(sub QI (sll QI 1 8) 1))))
(set result7
(if QI
(lt (subword HI rn 0) 0)
0
(if QI
(lt (subword HI rn 0) (sll DI 1 8))
(subword HI rn 0)
(sub QI (sll QI 1 8) 1))))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0x7 | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 1))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 1)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0xb | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 2))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 2)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0xf | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 3))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 3)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x3 | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 4))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 4)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x7 | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 5))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 5)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0xb | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 6))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 6)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0xf | rn | rd | 0x0 |
(sequence
((QI count) (DI mask) (DI rhs))
(set count (mul QI 8 7))
(set mask (sll DI (inv INT 0) count))
(set rhs (srl DI (and DI rm mask) count))
(set count (mul QI 8 (sub QI 8 7)))
(set mask (srl DI (inv INT 0) count))
(set rd
(or DI rhs (sll DI (and DI rn mask) count))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x12 | rm | 0x1 | rn | rd | 0x0 |
(sequence
((SI temp) (SI result1) (SI result0))
(set result0 (subword SI rd 1))
(set result1 (subword SI rd 0))
(set temp
(mul SI
(zext SI (subword HI rm 3))
(zext SI (subword HI rn 3))))
(set temp
(if SI
(lt (sll DI temp 1)
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sll DI temp 1) (sll DI 1 (sub INT 32 1)))
(sll DI temp 1)
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result0
(if SI
(lt (add DI (ext DI result0) (ext DI temp))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (add DI (ext DI result0) (ext DI temp))
(sll DI 1 (sub INT 32 1)))
(add DI (ext DI result0) (ext DI temp))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 2))
(zext SI (subword HI rn 2))))
(set temp
(if SI
(lt (sll DI temp 1)
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sll DI temp 1) (sll DI 1 (sub INT 32 1)))
(sll DI temp 1)
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result1
(if SI
(lt (add DI (ext DI result1) (ext DI temp))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (add DI (ext DI result1) (ext DI temp))
(sll DI 1 (sub INT 32 1)))
(add DI (ext DI result1) (ext DI temp))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 | 10 11 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-ext | f-right | f-right | f-dest | f-rsvd |
| 0x12 | 0x5 | rn | rn | rd | 0x0 |
(sequence
((SI temp) (SI result1) (SI result0))
(set result0 (subword SI rd 1))
(set result1 (subword SI rd 0))
(set temp
(mul SI
(zext SI (subword HI rm 3))
(zext SI (subword HI rn 3))))
(set temp
(if SI
(lt (sll DI temp 1)
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sll DI temp 1) (sll DI 1 (sub INT 32 1)))
(sll DI temp 1)
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result0
(if SI
(lt (sub DI (ext DI result0) (ext DI temp))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sub DI (ext DI result0) (ext DI temp))
(sll DI 1 (sub INT 32 1)))
(sub DI (ext DI result0) (ext DI temp))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 2))
(zext SI (subword HI rn 2))))
(set temp
(if SI
(lt (sll DI temp 1)
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sll DI temp 1) (sll DI 1 (sub INT 32 1)))
(sll DI temp 1)
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result1
(if SI
(lt (sub DI (ext DI result1) (ext DI temp))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sub DI (ext DI result1) (ext DI temp))
(sll DI 1 (sub INT 32 1)))
(sub DI (ext DI result1) (ext DI temp))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0x6 | rn | rd | 0x0 |
(sequence
((DI temp) (SI result0) (SI result1))
(set temp
(mul DI
(zext DI (subword SI rm 1))
(zext DI (subword SI rn 1))))
(set result0
(if SI
(lt (sra DI temp 31)
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sra DI temp 31) (sll DI 1 (sub INT 32 1)))
(sra DI temp 31)
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set temp
(mul DI
(zext DI (subword SI rm 0))
(zext DI (subword SI rn 0))))
(set result1
(if SI
(lt (sra DI temp 31)
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sra DI temp 31) (sll DI 1 (sub INT 32 1)))
(sra DI temp 31)
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0x9 | rn | rd | 0x0 |
(sequence
((SI temp)
(HI result0)
(HI result1)
(HI result2)
(HI result3)
(HI c))
(set c (sll INT 1 14))
(set temp
(mul SI
(zext SI (subword HI rm 3))
(zext SI (subword HI rn 3))))
(set result0
(if HI
(lt (sra SI (add SI temp c) 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI (add SI temp c) 15)
(sll DI 1 (sub INT 16 1)))
(sra SI (add SI temp c) 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 2))
(zext SI (subword HI rn 2))))
(set result1
(if HI
(lt (sra SI (add SI temp c) 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI (add SI temp c) 15)
(sll DI 1 (sub INT 16 1)))
(sra SI (add SI temp c) 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 1))
(zext SI (subword HI rn 1))))
(set result2
(if HI
(lt (sra SI (add SI temp c) 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI (add SI temp c) 15)
(sll DI 1 (sub INT 16 1)))
(sra SI (add SI temp c) 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 0))
(zext SI (subword HI rn 0))))
(set result3
(if HI
(lt (sra SI (add SI temp c) 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI (add SI temp c) 15)
(sll DI 1 (sub INT 16 1)))
(sra SI (add SI temp c) 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0x5 | rn | rd | 0x0 |
(sequence
((SI temp)
(HI result0)
(HI result1)
(HI result2)
(HI result3))
(set temp
(mul SI
(zext SI (subword HI rm 3))
(zext SI (subword HI rn 3))))
(set result0
(if HI
(lt (sra SI temp 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI temp 15) (sll DI 1 (sub INT 16 1)))
(sra SI temp 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 2))
(zext SI (subword HI rn 2))))
(set result1
(if HI
(lt (sra SI temp 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI temp 15) (sll DI 1 (sub INT 16 1)))
(sra SI temp 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 1))
(zext SI (subword HI rn 1))))
(set result2
(if HI
(lt (sra SI temp 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI temp 15) (sll DI 1 (sub INT 16 1)))
(sra SI temp 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set temp
(mul SI
(zext SI (subword HI rm 0))
(zext SI (subword HI rn 0))))
(set result3
(if HI
(lt (sra SI temp 15)
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sra SI temp 15) (sll DI 1 (sub INT 16 1)))
(sra SI temp 15)
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0xe | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(mul SI
(zext SI (subword HI rm 1))
(zext SI (subword HI rn 1))))
(set result1
(mul SI
(zext SI (subword HI rm 0))
(zext SI (subword HI rn 0))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0x2 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(mul SI (subword SI rm 1) (subword SI rn 1)))
(set result1
(mul SI (subword SI rm 0) (subword SI rn 0)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0xa | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(mul SI
(zext SI (subword HI rm 3))
(zext SI (subword HI rn 3))))
(set result1
(mul SI
(zext SI (subword HI rm 2))
(zext SI (subword HI rn 2))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x12 | rm | 0x9 | rn | rd | 0x0 |
(sequence
((DI acc))
(set acc
(mul SI
(zext SI (subword HI rm 0))
(zext SI (subword HI rn 0))))
(set acc
(add DI
acc
(mul SI
(zext SI (subword HI rm 1))
(zext SI (subword HI rn 1)))))
(set acc
(add DI
acc
(mul SI
(zext SI (subword HI rm 2))
(zext SI (subword HI rn 2)))))
(set acc
(add DI
acc
(mul SI
(zext SI (subword HI rm 3))
(zext SI (subword HI rn 3)))))
(set rd (add DI rd acc)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x13 | rm | 0x1 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(mul HI (subword HI rm 3) (subword HI rn 3)))
(set result1
(mul HI (subword HI rm 2) (subword HI rn 2)))
(set result2
(mul HI (subword HI rm 1) (subword HI rn 1)))
(set result3
(mul HI (subword HI rm 0) (subword HI rn 0)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn64 | rm64 | 0x3 |
(set rn64 rm64)
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8x4 |
| 0xc7 | imm8x4 |
(set r0
(add UDI
(and UDI (add UDI pc 4) (inv INT 3))
imm8x4))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x0 |
(set (mem UQI rn) (subword UQI rm 3))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op8 | f-rm | f-imm4 |
| 0x84 | rm | imm4 |
(set r0 (ext SI (mem QI (add SI rm imm4))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x4 |
(sequence ((DI addr)) (set addr (sub SI rn 1)) (set (mem UQI addr) (subword UQI rm 3)) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0x4 |
(set (mem UQI (add SI r0 rn)) (subword UQI rm 3))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xc0 | imm8 |
(sequence ((DI addr)) (set addr (add SI gbr imm8)) (set (mem UQI addr) (subword UQI r0 3)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op8 | f-rm | f-imm4 |
| 0x80 | rm | imm4 |
(sequence ((DI addr)) (set addr (add SI rm imm4)) (set (mem UQI addr) (subword UQI r0 3)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x0 |
(set rn (ext SI (mem QI rm)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x4 |
(sequence
((QI data))
(set data (mem QI rm))
(if (eq (index-of rm) (index-of rn))
(set rm (ext SI data))
(set rm (add SI rm 1)))
(set rn (ext SI data)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0xc |
(set rn (ext SI (mem QI (add SI r0 rm))))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xc4 | imm8 |
(set r0 (ext SI (mem QI (add SI gbr imm8))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0xc3 |
(set (mem SI rn) r0)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x73 |
(set rn rn)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-imm16 | f-dest | f-rsvd |
| 0x33 | imm16 | rd | 0x0 |
(set rd (ext DI imm16))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-imm8 |
| 0xe | rn | imm8 |
(set rn (ext DI (and QI imm8 255)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 | 28 29 30 31 |
| f-op4 | f-rn | f-imm20 | f-sub4 |
| 0x0 | rn | imm20 | 0x0 |
(set rn imm20)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x2 |
(set (mem SI rn) rm)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-imm8x4 |
| 0xd | rn | imm8x4 |
(set rn
(mem SI
(add UINT
imm8x4
(and UDI (add UDI pc 4) (inv INT 3)))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-imm4x4 |
| 0x5 | rn | rm | imm4x4 |
(set rn (mem SI (add SI rm imm4x4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
| f-op4 | f-rn | f-rm | f-sub4 | f-16-4 | f-imm12x4 |
| 0x3 | rn | rm | 0x1 | 0x6 | imm12x4 |
(set rn (mem SI (add SI rm imm12x4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 | 16 17 18 19 | 20 21 22 23 24 25 26 27 28 29 30 31 |
| f-op4 | f-rn | f-rm | f-sub4 | f-16-4 | f-imm12x4 |
| 0x3 | rn | rm | 0x1 | 0x2 | imm12x4 |
(set (mem SI (add SI rn imm12x4)) rm)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x6 |
(sequence ((SI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) rm) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0x6 |
(set (mem SI (add SI r0 rn)) rm)
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8x4 |
| 0xc2 | imm8x4 |
(set (mem SI (add SI gbr imm8x4)) r0)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-imm4x4 |
| 0x1 | rn | rm | imm4x4 |
(set (mem SI (add SI rn imm4x4)) rm)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x2 |
(set rn (mem SI rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x6 |
(sequence
()
(set rn (mem SI rm))
(if (eq (index-of rm) (index-of rn))
(set rm rn)
(set rm (add SI rm 4))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0xe |
(set rn (mem SI (add SI r0 rm)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8x4 |
| 0xc6 | imm8x4 |
(set r0 (mem SI (add SI gbr imm8x4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x29 |
(set rn (zext SI tbit))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0xa9 |
(set r0 (c-call SI "sh64_movua" pc rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0xe9 |
(sequence () (set r0 (c-call SI "sh64_movua" pc rn)) (set rn (add SI rn 4)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x1 |
(set (mem HI rn) (subword HI rm 1))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-imm8x2 |
| 0x9 | rn | imm8x2 |
(set rn
(ext SI (mem HI (add UDI (add UDI pc 4) imm8x2))))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op8 | f-rm | f-imm4x2 |
| 0x85 | rm | imm4x2 |
(set r0 (ext SI (mem HI (add SI rm imm4x2))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x5 |
(sequence ((DI addr)) (set addr (sub SI rn 2)) (set (mem HI addr) (subword HI rm 1)) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0x5 |
(set (mem HI (add SI r0 rn)) (subword HI rm 1))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8x2 |
| 0xc1 | imm8x2 |
(set (mem HI (add SI gbr imm8x2))
(subword HI r0 1))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op8 | f-rm | f-imm4x2 |
| 0x81 | rm | imm4x2 |
(set (mem HI (add SI rm imm4x2))
(subword HI r0 1))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x1 |
(set rn (ext SI (mem HI rm)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x5 |
(sequence
((HI data))
(set data (mem HI rm))
(if (eq (index-of rm) (index-of rn))
(set rm (ext SI data))
(set rm (add SI rm 2)))
(set rn (ext SI data)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0xd |
(set rn (ext SI (mem HI (add SI r0 rm))))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8x2 |
| 0xc5 | imm8x2 |
(set r0 (ext SI (mem HI (add SI gbr imm8x2))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xa | rm | 0xd | rn | rd | 0x0 |
(sequence
((QI control)
(HI result3)
(HI result2)
(HI result1)
(HI result0))
(set control (and QI rn 255))
(set result0
(subword HI rm (sub INT 3 (and QI control 3))))
(set result1
(subword
HI
rm
(sub INT 3 (and QI (srl QI control 2) 3))))
(set result2
(subword
HI
rm
(sub INT 3 (and QI (srl QI control 4) 3))))
(set result3
(subword
HI
rm
(sub INT 3 (and QI (srl QI control 6) 3))))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x12 | rm | 0x0 | rn | rd | 0x0 |
(sequence
((DI acc))
(set acc
(abs DI
(sub QI (subword QI rm 0) (subword QI rn 0))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 1) (subword QI rn 1)))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 2) (subword QI rn 2)))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 3) (subword QI rn 3)))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 4) (subword QI rn 4)))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 5) (subword QI rn 5)))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 6) (subword QI rn 6)))))
(set acc
(add DI
acc
(abs QI
(sub QI (subword QI rm 7) (subword QI rn 7)))))
(set rd (add DI rd acc)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0x6 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(if SI
(lt (sll DI (subword SI rm 1) (and DI rn 31))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sll DI (subword SI rm 1) (and DI rn 31))
(sll DI 1 (sub INT 32 1)))
(sll DI (subword SI rm 1) (and DI rn 31))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result1
(if SI
(lt (sll DI (subword SI rm 0) (and DI rn 31))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sll DI (subword SI rm 0) (and DI rn 31))
(sll DI 1 (sub INT 32 1)))
(sll DI (subword SI rm 0) (and DI rn 31))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0x5 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(if HI
(lt (sll DI (subword HI rm 3) (and DI rn 15))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sll DI (subword HI rm 3) (and DI rn 15))
(sll DI 1 (sub INT 16 1)))
(sll DI (subword HI rm 3) (and DI rn 15))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result1
(if HI
(lt (sll DI (subword HI rm 2) (and DI rn 15))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sll DI (subword HI rm 2) (and DI rn 15))
(sll DI 1 (sub INT 16 1)))
(sll DI (subword HI rm 2) (and DI rn 15))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result2
(if HI
(lt (sll DI (subword HI rm 1) (and DI rn 15))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sll DI (subword HI rm 1) (and DI rn 15))
(sll DI 1 (sub INT 16 1)))
(sll DI (subword HI rm 1) (and DI rn 15))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result3
(if HI
(lt (sll DI (subword HI rm 0) (and DI rn 15))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sll DI (subword HI rm 0) (and DI rn 15))
(sll DI 1 (sub INT 16 1)))
(sll DI (subword HI rm 0) (and DI rn 15))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0xa | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(sra SI (subword SI rm 1) (and DI rn 31)))
(set result1
(sra SI (subword SI rm 0) (and DI rn 31)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0xb | rn | rd | 0x0 |
(set rd
(if DI
(lt (sra DI rm (and DI rn 63))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg DI (sll DI 1 (sub INT 16 1)))
(if DI
(lt (sra DI rm (and DI rn 63))
(sll DI 1 (sub INT 16 1)))
(sra DI rm (and DI rn 63))
(sub DI (sll DI 1 (sub INT 16 1)) 1))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0x9 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(sra HI (subword HI rm 3) (and DI rn 15)))
(set result1
(sra HI (subword HI rm 2) (and DI rn 15)))
(set result2
(sra HI (subword HI rm 1) (and DI rn 15)))
(set result3
(sra HI (subword HI rm 0) (and DI rn 15)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x4 | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0 (subword QI rm 3))
(set result1 (subword QI rn 3))
(set result2 (subword QI rm 2))
(set result3 (subword QI rn 2))
(set result4 (subword QI rm 1))
(set result5 (subword QI rn 1))
(set result6 (subword QI rm 0))
(set result7 (subword QI rn 0))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x6 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0 (subword SI rm 0))
(set result1 (subword SI rn 0))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x5 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0 (subword HI rm 1))
(set result1 (subword HI rn 1))
(set result2 (subword HI rm 0))
(set result3 (subword HI rn 0))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x0 | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0 (subword QI rm 7))
(set result1 (subword QI rn 7))
(set result2 (subword QI rm 6))
(set result3 (subword QI rn 6))
(set result4 (subword QI rm 5))
(set result5 (subword QI rn 5))
(set result6 (subword QI rm 4))
(set result7 (subword QI rn 4))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x2 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0 (subword SI rm 1))
(set result1 (subword SI rn 1))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0xb | rm | 0x1 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0 (subword HI rm 3))
(set result1 (subword HI rn 3))
(set result2 (subword HI rm 2))
(set result3 (subword HI rn 2))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0x2 | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(sll SI (subword SI rm 1) (and DI rn 31)))
(set result1
(sll SI (subword SI rm 0) (and DI rn 31)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0x1 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(sll HI (subword HI rm 3) (and DI rn 15)))
(set result1
(sll HI (subword HI rm 2) (and DI rn 15)))
(set result2
(sll HI (subword HI rm 1) (and DI rn 15)))
(set result3
(sll HI (subword HI rm 0) (and DI rn 15)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0xe | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(srl SI (subword SI rm 1) (and DI rn 31)))
(set result1
(srl SI (subword SI rm 0) (and DI rn 31)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x3 | rm | 0xd | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(srl HI (subword HI rm 3) (and DI rn 15)))
(set result1
(srl HI (subword HI rm 2) (and DI rn 15)))
(set result2
(srl HI (subword HI rm 1) (and DI rn 15)))
(set result3
(srl HI (subword HI rm 0) (and DI rn 15)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0xa | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(sub SI (subword SI rm 1) (subword SI rn 1)))
(set result1
(sub SI (subword SI rm 0) (subword SI rn 0)))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0xe | rn | rd | 0x0 |
(sequence
((SI result1) (SI result0))
(set result0
(if SI
(lt (sub DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1)))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sub DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1)))
(sll DI 1 (sub INT 32 1)))
(sub DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1)))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set result1
(if SI
(lt (sub DI
(ext DI (subword SI rm 0))
(ext DI (subword SI rn 0)))
(neg DI (sll DI 1 (sub INT 32 1))))
(neg SI (sll SI 1 (sub INT 32 1)))
(if SI
(lt (sub DI
(ext DI (subword SI rm 0))
(ext DI (subword SI rn 0)))
(sll DI 1 (sub INT 32 1)))
(sub DI
(ext DI (subword SI rm 0))
(ext DI (subword SI rn 0)))
(sub SI (sll SI 1 (sub INT 32 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result1) 32)
(zext DI result0))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0xc | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if QI
(lt (sub DI
(zext DI (subword QI rm 7))
(zext DI (subword QI rn 7)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 7))
(zext DI (subword QI rn 7)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 7))
(zext DI (subword QI rn 7)))
(sub QI (sll QI 1 8) 1))))
(set result1
(if QI
(lt (sub DI
(zext DI (subword QI rm 6))
(zext DI (subword QI rn 6)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 6))
(zext DI (subword QI rn 6)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 6))
(zext DI (subword QI rn 6)))
(sub QI (sll QI 1 8) 1))))
(set result2
(if QI
(lt (sub DI
(zext DI (subword QI rm 5))
(zext DI (subword QI rn 5)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 5))
(zext DI (subword QI rn 5)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 5))
(zext DI (subword QI rn 5)))
(sub QI (sll QI 1 8) 1))))
(set result3
(if QI
(lt (sub DI
(zext DI (subword QI rm 4))
(zext DI (subword QI rn 4)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 4))
(zext DI (subword QI rn 4)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 4))
(zext DI (subword QI rn 4)))
(sub QI (sll QI 1 8) 1))))
(set result4
(if QI
(lt (sub DI
(zext DI (subword QI rm 3))
(zext DI (subword QI rn 3)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 3))
(zext DI (subword QI rn 3)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 3))
(zext DI (subword QI rn 3)))
(sub QI (sll QI 1 8) 1))))
(set result5
(if QI
(lt (sub DI
(zext DI (subword QI rm 2))
(zext DI (subword QI rn 2)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 2))
(zext DI (subword QI rn 2)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 2))
(zext DI (subword QI rn 2)))
(sub QI (sll QI 1 8) 1))))
(set result6
(if QI
(lt (sub DI
(zext DI (subword QI rm 1))
(zext DI (subword QI rn 1)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 1))
(zext DI (subword QI rn 1)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 1))
(zext DI (subword QI rn 1)))
(sub QI (sll QI 1 8) 1))))
(set result7
(if QI
(lt (sub DI
(zext DI (subword QI rm 0))
(zext DI (subword QI rn 0)))
0)
0
(if QI
(lt (sub DI
(zext DI (subword QI rm 0))
(zext DI (subword QI rn 0)))
(sll DI 1 8))
(sub DI
(zext DI (subword QI rm 0))
(zext DI (subword QI rn 0)))
(sub QI (sll QI 1 8) 1))))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0xd | rn | rd | 0x0 |
(sequence
((QI result7)
(QI result6)
(QI result5)
(QI result4)
(QI result3)
(QI result2)
(QI result1)
(QI result0))
(set result0
(if HI
(lt (sub DI
(ext DI (subword QI rm 7))
(ext DI (subword QI rn 7)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 7))
(ext DI (subword QI rn 7)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 7))
(ext DI (subword QI rn 7)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result1
(if HI
(lt (sub DI
(ext DI (subword QI rm 6))
(ext DI (subword QI rn 6)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 6))
(ext DI (subword QI rn 6)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 6))
(ext DI (subword QI rn 6)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result2
(if HI
(lt (sub DI
(ext DI (subword QI rm 5))
(ext DI (subword QI rn 5)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 5))
(ext DI (subword QI rn 5)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 5))
(ext DI (subword QI rn 5)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result3
(if HI
(lt (sub DI
(ext DI (subword QI rm 4))
(ext DI (subword QI rn 4)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 4))
(ext DI (subword QI rn 4)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 4))
(ext DI (subword QI rn 4)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result4
(if HI
(lt (sub DI
(ext DI (subword QI rm 3))
(ext DI (subword QI rn 3)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 3))
(ext DI (subword QI rn 3)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 3))
(ext DI (subword QI rn 3)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result5
(if HI
(lt (sub DI
(ext DI (subword QI rm 2))
(ext DI (subword QI rn 2)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 2))
(ext DI (subword QI rn 2)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 2))
(ext DI (subword QI rn 2)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result6
(if HI
(lt (sub DI
(ext DI (subword QI rm 1))
(ext DI (subword QI rn 1)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 1))
(ext DI (subword QI rn 1)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 1))
(ext DI (subword QI rn 1)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set result7
(if HI
(lt (sub DI
(ext DI (subword QI rm 0))
(ext DI (subword QI rn 0)))
(neg DI (sll DI 1 (sub INT 16 1))))
(neg HI (sll HI 1 (sub INT 16 1)))
(if HI
(lt (sub DI
(ext DI (subword QI rm 0))
(ext DI (subword QI rn 0)))
(sll DI 1 (sub INT 16 1)))
(sub DI
(ext DI (subword QI rm 0))
(ext DI (subword QI rn 0)))
(sub HI (sll HI 1 (sub INT 16 1)) 1))))
(set rd
(or DI
(sll DI (zext DI result7) 56)
(or DI
(sll DI (zext DI result6) 48)
(or DI
(sll DI (zext DI result5) 40)
(or DI
(sll DI (zext DI result4) 32)
(or DI
(sll DI (zext DI result3) 24)
(or DI
(sll DI (zext DI result2) 16)
(or DI
(sll DI (zext DI result1) 8)
(zext DI result0))))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x2 | rm | 0x9 | rn | rd | 0x0 |
(sequence
((HI result3)
(HI result2)
(HI result1)
(HI result0))
(set result0
(sub HI (subword HI rm 3) (subword HI rn 3)))
(set result1
(sub HI (subword HI rm 2) (subword HI rn 2)))
(set result2
(sub HI (subword HI rm 1) (subword HI rn 1)))
(set result3
(sub HI (subword HI rm 0) (subword HI rn 0)))
(set rd
(or DI
(sll DI (zext DI result3) 48)
(or DI
(sll DI (zext DI result2) 32)
(or DI
(sll DI (zext DI result1) 16)
(zext DI result0))))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x0 | rn | rm | 0x7 |
(set macl (mul SI rm rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x80 |
(set rn (mul SI rn r0))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0xe | rn | rd | 0x0 |
(set rd
(mul DI
(ext DI (subword SI rm 1))
(ext DI (subword SI rn 1))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0xf |
(set macl
(mul SI
(ext SI (subword HI rm 1))
(ext SI (subword HI rn 1))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0xe | rn | rd | 0x0 |
(set rd
(mul DI
(zext DI (subword SI rm 1))
(zext DI (subword SI rn 1))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0xe |
(set macl
(mul SI
(zext SI (subword HI rm 1))
(zext SI (subword HI rn 1))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0xb |
(set rn (neg SI rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0xa |
(sequence ((BI flag)) (set flag (sub-cflag INT 0 rm tbit)) (set rn (subc INT 0 rm tbit)) (set tbit flag))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | 0x3f | 0x0 | 0x3f | 0x3f | 0x0 |
(nop)
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x9 |
(nop)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn64 | rm64 | 0x7 |
(set rn64 (inv DI rm64))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0xd | 0x3f | rd | 0x0 |
(set rd (c-call DI "sh64_nsb" rm))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6x32 | f-dest | f-rsvd |
| 0x38 | rm | 0x9 | disp6x32 | 0x3f | 0x0 |
(sequence () (set rm rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x93 |
(sequence () (set rn rn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6x32 | f-dest | f-rsvd |
| 0x38 | rm | 0x8 | disp6x32 | 0x3f | 0x0 |
(sequence () (set rm rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0xa3 |
(sequence () (set rn rn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6x32 | f-dest | f-rsvd |
| 0x38 | rm | 0xc | disp6x32 | 0x3f | 0x0 |
(sequence () (set rm rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0xb3 |
(sequence () (set rn rn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x9 | rn | rd | 0x0 |
(set rd (or DI rm rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn64 | rm64 | 0xb |
(set rn64 (or DI rm64 rn64))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xcf | imm8 |
(sequence ((DI addr) (UQI data)) (set addr (add SI r0 gbr)) (set data (or UQI (mem UQI addr) imm8)) (set (mem UQI addr) data))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-imm10 | f-dest | f-rsvd |
| 0x37 | rm | imm10 | rd | 0x0 |
(set rd (or DI rm (ext DI imm10)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xcb | uimm8 |
(set r0 (or SI r0 (zext DI uimm8)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x83 |
(c-call VOID "sh64_pref" rn)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6x32 | f-right | f-rsvd |
| 0x38 | rm | 0x1 | disp6x32 | 0x3f | 0x0 |
(sequence () (set rm rm))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-disp16 | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x3a | disp16 | likely | 0x0 | tra | 0x0 |
(sequence () (set tra (add INT disp16 1)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x1a | 0x3f | 0x1 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (set tra rn))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-disp16 | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x3b | disp16 | likely | 0x0 | tra | 0x0 |
(sequence () (set tra disp16))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 | 23 24 | 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-likely | f-23-2 | f-tra | f-rsvd |
| 0x1a | 0x3f | 0x5 | rn | likely | 0x0 | tra | 0x0 |
(sequence () (set tra (add UDI pc rn)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x38 | rm | 0xf | disp6 | rd | 0x0 |
(sequence ((SI address)) (set address (add DI rm disp6)) (set (mem SI address) rd))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | rm | 0xf | 0x3f | crj | 0x0 |
(set crj rm)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x24 |
(sequence ((BI temp)) (set temp (srl SI rn 31)) (set rn (or SI (sll SI rn 1) tbit)) (set tbit (if BI temp 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x25 |
(sequence ((BI lsbit) (SI temp)) (set lsbit (if BI (eq (and SI rn 1) 0) 0 1)) (set temp tbit) (set rn (or SI (srl SI rn 1) (sll SI temp 31))) (set tbit (if BI lsbit 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x4 |
(sequence ((BI temp)) (set temp (srl SI rn 31)) (set rn (or SI (sll SI rn 1) temp)) (set tbit (if BI temp 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x5 |
(sequence ((BI lsbit) (SI temp)) (set lsbit (if BI (eq (and SI rn 1) 0) 0 1)) (set temp lsbit) (set rn (or SI (srl SI rn 1) (sll SI temp 31))) (set tbit (if BI lsbit 1 0)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | 0x3f | 0x3 | 0x3f | 0x3f | 0x0 |
(nop)
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0xb |
(sequence () (set pc (add UDI pc 2)) (delay VOID 1 (set pc pr)))
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x58 |
(set sbit 1)
| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
| f-op16 |
| 0x18 |
(set tbit 1)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x4 | rn | rm | 0xc |
(sequence
((SI shamt))
(set shamt (and SI rm 31))
(if (ge rm 0)
(set rn (sll SI rn shamt))
(if (ne shamt 0)
(set rn (sra SI rn (sub INT 32 shamt)))
(if (lt rn 0) (set rn (neg INT 1)) (set rn 0)))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x20 |
(sequence ((BI t)) (set t (srl SI rn 31)) (set rn (sll SI rn 1)) (set tbit (if BI t 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x21 |
(sequence ((BI t)) (set t (and SI rn 1)) (set rn (sra SI rn 1)) (set tbit (if BI t 1 0)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x7 | rn | rd | 0x0 |
(set rd (sra DI rm (and DI rn 63)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x6 | rn | rd | 0x0 |
(set rd
(ext DI
(sra SI (subword SI rm 1) (and DI rn 63))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-uimm6 | f-dest | f-rsvd |
| 0x31 | rm | 0x7 | uimm6 | rd | 0x0 |
(set rd (sra DI rm uimm6))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-uimm6 | f-dest | f-rsvd |
| 0x31 | rm | 0x6 | uimm6 | rd | 0x0 |
(set rd
(ext DI
(sra SI (subword SI rm 1) (and UINT uimm6 63))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x4 | rn | rm | 0xd |
(sequence
((SI shamt))
(set shamt (and SI rm 31))
(if (ge rm 0)
(set rn (sll SI rn shamt))
(if (ne shamt 0)
(set rn (srl SI rn (sub INT 32 shamt)))
(set rn 0))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x0 |
(sequence ((BI t)) (set t (srl SI rn 31)) (set rn (sll SI rn 1)) (set tbit (if BI t 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x28 |
(set rn (sll SI rn 16))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x8 |
(set rn (sll SI rn 2))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x18 |
(set rn (sll SI rn 8))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x1 | rn | rd | 0x0 |
(set rd (sll DI rm (and DI rn 63)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x0 | rn | rd | 0x0 |
(set rd
(ext DI
(sll SI (subword SI rm 1) (and DI rn 63))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-uimm6 | f-dest | f-rsvd |
| 0x31 | rm | 0x1 | uimm6 | rd | 0x0 |
(set rd (sll DI rm uimm6))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-uimm6 | f-dest | f-rsvd |
| 0x31 | rm | 0x0 | uimm6 | rd | 0x0 |
(set rd
(ext DI
(sll SI (subword SI rm 1) (and UINT uimm6 63))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x1 |
(sequence ((BI t)) (set t (and SI rn 1)) (set rn (srl SI rn 1)) (set tbit (if BI t 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x29 |
(set rn (srl SI rn 16))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x9 |
(set rn (srl SI rn 2))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x19 |
(set rn (srl SI rn 8))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x3 | rn | rd | 0x0 |
(set rd (srl DI rm (and DI rn 63)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0x2 | rn | rd | 0x0 |
(set rd
(ext DI
(srl SI (subword SI rm 1) (and DI rn 63))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-uimm6 | f-dest | f-rsvd |
| 0x31 | rm | 0x3 | uimm6 | rd | 0x0 |
(set rd (srl DI rm uimm6))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-uimm6 | f-dest | f-rsvd |
| 0x31 | rm | 0x2 | uimm6 | rd | 0x0 |
(set rd
(ext DI
(srl SI (subword SI rm 1) (and UINT uimm6 63))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-uimm16 | f-dest | f-rsvd |
| 0x32 | uimm16 | rd | 0x0 |
(set rd (or DI (sll DI rd 16) (zext DI uimm16)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | 0x3f | 0x7 | 0x3f | 0x3f | 0x0 |
(nop)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10 | f-dest | f-rsvd |
| 0x28 | rm | disp10 | rd | 0x0 |
(set (mem UQI (add DI rm (ext DI disp10)))
(and QI rd 255))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x12 |
(set rn gbr)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x22 |
(set rn vbr)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x13 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) gbr) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x23 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) vbr) (set rn addr))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x38 | rm | 0x6 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (DI val))
(set addr (add DI rm disp6))
(set bytecount (add DI (and DI addr 3) 1))
(if (and QI bytecount 4)
(set (mem SI (and DI addr -4)) rd)
(if endian
(sequence
()
(set val rd)
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8))))
(if (and QI bytecount 2)
(sequence
()
(set (mem HI (and DI addr -4))
(and HI val 65535))
(set val (srl DI val 16)))))
(sequence
()
(set val
(srl DI rd (sub INT 32 (mul INT 8 bytecount))))
(if (and QI bytecount 2)
(sequence
()
(set (mem HI (and DI addr -4))
(and HI val 65535))
(set val (srl DI val 16))))
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x38 | rm | 0x7 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (DI val))
(set addr (add DI rm disp6))
(set bytecount (add DI (and DI addr 7) 1))
(if (and QI bytecount 8)
(set (mem DI (and DI addr -8)) rd)
(if endian
(sequence
()
(set val rd)
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8))))
(if (and QI bytecount 2)
(sequence
()
(set (mem HI (and DI addr -4))
(and HI val 65535))
(set val (srl DI val 16))))
(if (and QI bytecount 4)
(sequence
()
(set (mem SI (and DI addr -8))
(and SI val 4294967295))
(set val (srl DI val 32)))))
(sequence
()
(set val
(srl DI rd (sub INT 64 (mul INT 8 bytecount))))
(if (and QI bytecount 4)
(sequence
()
(set (mem SI (and DI addr -8))
(and SI val 4294967295))
(set val (srl DI val 32))))
(if (and QI bytecount 2)
(sequence
()
(set (mem HI (and DI addr -4))
(and HI val 65535))
(set val (srl DI val 16))))
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x4 | f-dest | f-rsvd |
| 0x2a | rm | disp10x4 | rd | 0x0 |
(set (mem SI (add DI rm (ext DI disp10x4)))
(and SI rd 4294967295))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x38 | rm | 0x2 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (DI val))
(set addr (add DI rm disp6))
(set bytecount (sub INT 4 (and DI addr 3)))
(if (and QI bytecount 4)
(set (mem USI addr) rd)
(if endian
(sequence
()
(set val
(srl DI rd (sub INT 32 (mul INT 8 bytecount))))
(if (and QI bytecount 2)
(sequence
()
(set (mem UHI (and DI (add DI addr 1) -2))
(and HI val 65535))
(set val (srl DI val 16))))
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8)))))
(sequence
()
(set val rd)
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8))))
(if (and QI bytecount 2)
(sequence
()
(set (mem UHI (and DI (add DI addr 1) -2))
(and HI val 65535))
(set val (srl DI val 16))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-disp6 | f-dest | f-rsvd |
| 0x38 | rm | 0x3 | disp6 | rd | 0x0 |
(sequence
((DI addr) (QI bytecount) (DI val))
(set addr (add DI rm disp6))
(set bytecount (sub INT 8 (and DI addr 7)))
(if (and QI bytecount 8)
(set (mem UDI addr) rd)
(if endian
(sequence
()
(set val
(srl DI rd (sub INT 64 (mul INT 8 bytecount))))
(if (and QI bytecount 4)
(sequence
()
(set (mem USI (and DI (add DI addr 3) -4))
(and SI val 4294967295))
(set val (srl DI val 32))))
(if (and QI bytecount 2)
(sequence
()
(set (mem UHI (and DI (add DI addr 1) -2))
(and HI val 65535))
(set val (srl DI val 16))))
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8)))))
(sequence
()
(set val rd)
(if (and QI bytecount 1)
(sequence
()
(set (mem UQI addr) (and QI val 255))
(set val (srl DI val 8))))
(if (and QI bytecount 2)
(sequence
()
(set (mem UHI (and DI (add DI addr 1) -2))
(and HI val 65535))
(set val (srl DI val 16))))
(if (and QI bytecount 4)
(sequence
()
(set (mem USI (and DI (add DI addr 3) -4))
(and SI val 4294967295))
(set val (srl DI val 32))))))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x8 | f-dest | f-rsvd |
| 0x2b | rm | disp10x8 | rd | 0x0 |
(set (mem DI (add DI rm (ext DI disp10x8))) rd)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x6a |
(set rn fpscr)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x5a |
(set rn (subword SI fpul 0))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0xa |
(set rn mach)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x1a |
(set rn macl)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x0 | rn | 0x2a |
(set rn pr)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x62 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) fpscr) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x52 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SF addr) fpul) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x2 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) mach) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x12 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) macl) (set rn addr))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x22 |
(sequence ((DI addr)) (set addr (sub SI rn 4)) (set (mem SI addr) pr) (set rn addr))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-disp10x2 | f-dest | f-rsvd |
| 0x29 | rm | disp10x2 | rd | 0x0 |
(set (mem HI (add DI rm (ext DI disp10x2)))
(and HI rd 65535))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x18 | rm | 0x0 | rn | rd | 0x0 |
(set (mem UQI (add DI rm rn)) (subword QI rd 7))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x18 | rm | 0x2 | rn | rd | 0x0 |
(set (mem SI (add DI rm rn)) (subword SI rd 1))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x18 | rm | 0x3 | rn | rd | 0x0 |
(set (mem DI (add DI rm rn)) rd)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x18 | rm | 0x1 | rn | rd | 0x0 |
(set (mem HI (add DI rm rn)) (subword HI rd 3))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0xb | rn | rd | 0x0 |
(set rd (sub DI rm rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0x8 |
(set rn (sub SI rn rm))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0xa |
(sequence ((BI flag)) (set flag (sub-cflag SI rn rm tbit)) (set rn (subc SI rn rm tbit)) (set tbit flag))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x0 | rm | 0xa | rn | rd | 0x0 |
(set rd
(ext DI
(sub SI (subword SI rm 1) (subword SI rn 1))))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x3 | rn | rm | 0xb |
(sequence ((BI t)) (set t (sub-oflag SI rn rm 0)) (set rn (sub SI rn rm)) (set tbit (if BI t 1 0)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x8 |
(sequence
((UHI top-half) (UQI byte1) (UQI byte0))
(set top-half (subword HI rm 0))
(set byte1 (subword QI rm 2))
(set byte0 (subword QI rm 3))
(set rn
(or SI
(sll SI top-half 16)
(or SI (sll SI byte0 8) byte1))))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x8 | rm | 0x3 | rn | rd | 0x0 |
(sequence ((DI addr) (DI temp)) (set addr (add DI rm rn)) (set temp (mem DI addr)) (set (mem DI addr) rd) (set rd temp))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x6 | rn | rm | 0x9 |
(set rn (or SI (srl SI rm 16) (sll SI rm 16)))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | 0x3f | 0x2 | 0x3f | 0x3f | 0x0 |
(nop)
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | 0x3f | 0x6 | 0x3f | 0x3f | 0x0 |
(nop)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op4 | f-rn | f-sub8 |
| 0x4 | rn | 0x1b |
(sequence ((UQI byte)) (set byte (mem UQI rn)) (set tbit (if BI (eq byte 0) 1 0)) (set byte (or UQI byte 128)) (set (mem UQI rn) byte))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1b | rm | 0x1 | 0x3f | 0x3f | 0x0 |
(c-call VOID "sh64_trapa" rm pc)
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xc3 | uimm8 |
(c-call VOID "sh64_compact_trapa" uimm8 pc)
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0x8 |
(set tbit (if BI (eq (and SI rm rn) 0) 1 0))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xcc | imm8 |
(sequence
((DI addr))
(set addr (add SI r0 gbr))
(set tbit
(if BI (eq (and UQI (mem UQI addr) imm8) 0) 1 0)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xc8 | uimm8 |
(set tbit
(if BI (eq (and SI r0 (zext SI uimm8)) 0) 1 0))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x1 | rm | 0xd | rn | rd | 0x0 |
(set rd (xor DI rm rn))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn64 | rm64 | 0xa |
(set rn64 (xor DI rn64 rm64))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xce | imm8 |
(sequence ((DI addr) (UQI data)) (set addr (add SI r0 gbr)) (set data (xor UQI (mem UQI addr) imm8)) (set (mem UQI addr) data))
| 0 1 2 3 4 5 | 6 7 8 9 10 11 | 12 13 14 15 | 16 17 18 19 20 21 | 22 23 24 25 26 27 | 28 29 30 31 |
| f-op | f-left | f-ext | f-right | f-dest | f-rsvd |
| 0x31 | rm | 0xd | rn | rd | 0x0 |
(set rd (xor DI rm (ext DI imm6)))
| 0 1 2 3 4 5 6 7 | 8 9 10 11 12 13 14 15 |
| f-op8 | f-imm8 |
| 0xca | uimm8 |
(set r0 (xor SI r0 (zext DI uimm8)))
| 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 12 13 14 15 |
| f-op4 | f-rn | f-rm | f-sub4 |
| 0x2 | rn | rm | 0xd |
(set rn (or SI (sll SI rm 16) (srl SI rn 16)))
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/