EPIPHANY Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
EPIPHANY Architecture
This section describes various things about the cgen description of
the EPIPHANY architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): lsb = 0
ISA description
-
epiphany - Adapteva, Inc. EPIPHANY32 ISA
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist: 3 2 1 0
- decode-splits:
CPU Families
-
epiphanybf - Adapteva, Inc. EPIPHANY Family
Machines:
-
epiphany32 - Adapteva EPIPHANY
Models:
-
epiphany32 - Adapteva EPIPHANY 32/16
-
epiphanymf - Adapteva, Inc. EPIPHANY Family
Machines:
Machine variants
epiphany32 - Adapteva EPIPHANY
-
bfd-name: epiphany32
-
isas: epiphany
Model variants
epiphany32 - Adapteva EPIPHANY 32/16
Registers
h-arithmetic-modebit0 - arithmetic mode bit0
-
machines: base
-
bitsize: 1
h-arithmetic-modebit1 - arithmetic mode bit1
-
machines: base
-
bitsize: 1
h-arithmetic-modebit2 - arithmetic mode bit2
-
machines: base
-
bitsize: 1
h-bcbit - floating point carry bit
-
machines: base
-
bitsize: 1
h-bibit - floating point invalid bit
-
machines: base
-
bitsize: 1
h-bisbit - floating point invalid sticky
-
machines: base
-
bitsize: 1
h-bnbit - floating point neg bit
-
machines: base
-
bitsize: 1
h-bubit - floating point underfl bit
-
machines: base
-
bitsize: 1
h-busbit - floating point underflow sticky
-
machines: base
-
bitsize: 1
h-bvbit - floating point ovfl bit
-
machines: base
-
bitsize: 1
h-bvsbit - floating point overflow sticky
-
machines: base
-
bitsize: 1
h-bzbit - floating point zero bit
-
machines: base
-
bitsize: 1
h-caibit - core active indicator mode bit
-
machines: base
-
bitsize: 1
h-cbit - integer carry bit
-
machines: base
-
bitsize: 1
h-clockGateEnbit - clock gating enable bkpt enable
-
machines: base
-
bitsize: 1
h-core-registers - Special Core Registers
-
machines: base
-
bitsize: 32
-
array: [17]
names:
config |
0 |
status |
1 |
pc |
2 |
debug |
3 |
iab |
4 |
lc |
5 |
ls |
6 |
le |
7 |
iret |
8 |
imask |
9 |
ilat |
10 |
ilatst |
11 |
ilatcl |
12 |
ipend |
13 |
ctimer0 |
14 |
ctimer1 |
15 |
hstatus |
16 |
h-coreCfgResBit12 - core config bit 12
-
machines: base
-
bitsize: 1
h-coreCfgResBit13 - core config bit 13
-
machines: base
-
bitsize: 1
h-coreCfgResBit14 - core config bit 14
-
machines: base
-
bitsize: 1
h-coreCfgResBit15 - core config bit 15
-
machines: base
-
bitsize: 1
h-coreCfgResBit16 - core config bit 16
-
machines: base
-
bitsize: 1
h-coreCfgResBit20 - core config bit 20
-
machines: base
-
bitsize: 1
h-coreCfgResBit21 - core config bit 21
-
machines: base
-
bitsize: 1
h-coreCfgResBit24 - core config bit 24
-
machines: base
-
bitsize: 1
h-coreCfgResBit25 - core config bit 25
-
machines: base
-
bitsize: 1
h-coreCfgResBit26 - core config bit 26
-
machines: base
-
bitsize: 1
h-coreCfgResBit27 - core config bit 27
-
machines: base
-
bitsize: 1
h-coreCfgResBit28 - core config bit 28
-
machines: base
-
bitsize: 1
h-coreCfgResBit29 - core config bit 29
-
machines: base
-
bitsize: 1
h-coreCfgResBit30 - core config bit 30
-
machines: base
-
bitsize: 1
h-coreCfgResBit31 - core config bit 31
-
machines: base
-
bitsize: 1
h-coredma-registers - DMA registers in MMR space
-
machines: base
-
bitsize: 32
-
array: [16]
names:
dma0config |
0 |
dma0stride |
1 |
dma0count |
2 |
dma0srcaddr |
3 |
dma0dstaddr |
4 |
dma0auto0 |
5 |
dma0auto1 |
6 |
dma0status |
7 |
dma1config |
8 |
dma1stride |
9 |
dma1count |
10 |
dma1srcaddr |
11 |
dma1dstaddr |
12 |
dma1auto0 |
13 |
dma1auto1 |
14 |
dma1status |
15 |
h-coremem-registers - MEM registers in MMR space
-
machines: base
-
bitsize: 32
-
array: [4]
names:
memconfig |
0 |
memstatus |
1 |
memprotect |
2 |
memreserve |
3 |
h-coremesh-registers - MESH registers in MMR space
-
machines: base
-
bitsize: 32
-
array: [4]
names:
meshconfig |
0 |
coreid |
1 |
meshmulticast |
2 |
swreset |
3 |
h-expcause0bit - exceprion cause bit0
-
machines: base
-
bitsize: 1
h-expcause1bit - exceprion cause bit1
-
machines: base
-
bitsize: 1
h-expcause2bit - external load stalled bit
-
machines: base
-
bitsize: 1
h-extFstallbit - external fetch stalled bit
-
machines: base
-
bitsize: 1
h-fpregisters - all GPRs as float values
-
machines: base
-
bitsize: 32
-
array: [64]
names:
fp |
11 |
sp |
13 |
lr |
14 |
r0 |
0 |
r1 |
1 |
r2 |
2 |
r3 |
3 |
r4 |
4 |
r5 |
5 |
r6 |
6 |
r7 |
7 |
r8 |
8 |
r9 |
9 |
r10 |
10 |
r11 |
11 |
r12 |
12 |
r13 |
13 |
r14 |
14 |
r15 |
15 |
r16 |
16 |
r17 |
17 |
r18 |
18 |
r19 |
19 |
r20 |
20 |
r21 |
21 |
r22 |
22 |
r23 |
23 |
r24 |
24 |
r25 |
25 |
r26 |
26 |
r27 |
27 |
r28 |
28 |
r29 |
29 |
r30 |
30 |
r31 |
31 |
r32 |
32 |
r33 |
33 |
r34 |
34 |
r35 |
35 |
r36 |
36 |
r37 |
37 |
r38 |
38 |
r39 |
39 |
r40 |
40 |
r41 |
41 |
r42 |
42 |
r43 |
43 |
r44 |
44 |
r45 |
45 |
r46 |
46 |
r47 |
47 |
r48 |
48 |
r49 |
49 |
r50 |
50 |
r51 |
51 |
r52 |
52 |
r53 |
53 |
r54 |
54 |
r55 |
55 |
r56 |
56 |
r57 |
57 |
r58 |
58 |
r59 |
59 |
r60 |
60 |
r61 |
61 |
r62 |
62 |
r63 |
63 |
a1 |
0 |
a2 |
1 |
a3 |
2 |
a4 |
3 |
v1 |
4 |
v2 |
5 |
v3 |
6 |
v4 |
7 |
v5 |
8 |
v6 |
9 |
v7 |
10 |
v8 |
11 |
sb |
9 |
sl |
10 |
ip |
12 |
h-gidisablebit - global interrupt disable bit
-
machines: base
-
bitsize: 1
h-invExcEnbit - invalid exception enable bit
-
machines: base
-
bitsize: 1
h-kmbit - kernel mode bit
-
machines: base
-
bitsize: 1
h-mbkptEnbit - multicore bkpt enable
-
machines: base
-
bitsize: 1
h-memaddr - memory effective address
-
machines: base
-
bitsize: 32
h-nbit - integer neg bit
-
machines: base
-
bitsize: 1
h-ovfExcEnbit - overflow exception enable bit
-
machines: base
-
bitsize: 1
h-pc - program counter
-
machines: base
-
bitsize: 32
h-registers - all addressable registers
-
machines: base
-
bitsize: 32
-
array: [64]
names:
fp |
11 |
sp |
13 |
lr |
14 |
r0 |
0 |
r1 |
1 |
r2 |
2 |
r3 |
3 |
r4 |
4 |
r5 |
5 |
r6 |
6 |
r7 |
7 |
r8 |
8 |
r9 |
9 |
r10 |
10 |
r11 |
11 |
r12 |
12 |
r13 |
13 |
r14 |
14 |
r15 |
15 |
r16 |
16 |
r17 |
17 |
r18 |
18 |
r19 |
19 |
r20 |
20 |
r21 |
21 |
r22 |
22 |
r23 |
23 |
r24 |
24 |
r25 |
25 |
r26 |
26 |
r27 |
27 |
r28 |
28 |
r29 |
29 |
r30 |
30 |
r31 |
31 |
r32 |
32 |
r33 |
33 |
r34 |
34 |
r35 |
35 |
r36 |
36 |
r37 |
37 |
r38 |
38 |
r39 |
39 |
r40 |
40 |
r41 |
41 |
r42 |
42 |
r43 |
43 |
r44 |
44 |
r45 |
45 |
r46 |
46 |
r47 |
47 |
r48 |
48 |
r49 |
49 |
r50 |
50 |
r51 |
51 |
r52 |
52 |
r53 |
53 |
r54 |
54 |
r55 |
55 |
r56 |
56 |
r57 |
57 |
r58 |
58 |
r59 |
59 |
r60 |
60 |
r61 |
61 |
r62 |
62 |
r63 |
63 |
a1 |
0 |
a2 |
1 |
a3 |
2 |
a4 |
3 |
v1 |
4 |
v2 |
5 |
v3 |
6 |
v4 |
7 |
v5 |
8 |
v6 |
9 |
v7 |
10 |
v8 |
11 |
sb |
9 |
sl |
10 |
ip |
12 |
h-sflagbit - sflag bit
-
machines: base
-
bitsize: 1
h-timer0bit0 - timer 0 mode selection 0
-
machines: base
-
bitsize: 1
h-timer0bit1 - timer 0 mode selection 1
-
machines: base
-
bitsize: 1
h-timer0bit2 - timer 0 mode selection 2
-
machines: base
-
bitsize: 1
h-timer0bit3 - timer 0 mode selection 3
-
machines: base
-
bitsize: 1
h-timer1bit0 - timer 1 mode selection 0
-
machines: base
-
bitsize: 1
h-timer1bit1 - timer 1 mode selection 1
-
machines: base
-
bitsize: 1
h-timer1bit2 - timer 1 mode selection 2
-
machines: base
-
bitsize: 1
h-timer1bit3 - timer 1 mode selection 3
-
machines: base
-
bitsize: 1
h-trmbit - 0=round to nearest, 1=trunacte select bit
-
machines: base
-
bitsize: 1
h-unExcEnbit - underflow exception enablebit
-
machines: base
-
bitsize: 1
h-vbit - integer overflow bit
-
machines: base
-
bitsize: 1
h-vsbit - integer overflow sticky
-
machines: base
-
bitsize: 1
h-zbit - integer zero bit
-
machines: base
-
bitsize: 1
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/