IQ2000 Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
IQ2000 Architecture
This section describes various things about the cgen description of
the IQ2000 architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): lsb = 0
ISA description
-
iq2000 - Basic IQ2000 instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist: 31 30 29 28 27 26
- decode-splits:
CPU Families
-
iq10bf - IQ10 coprocessor family
Machines:
-
iq10 - IQ10 coprocessor
Models:
-
iq2000bf - IQ2000 family
Machines:
-
iq2000 - IQ2000 packet processing engine
Models:
-
iq2000 - IQ2000 microprocessor
Machine variants
iq10 - IQ10 coprocessor
-
bfd-name: iq10
-
isas: iq2000
iq2000 - IQ2000 packet processing engine
-
bfd-name: iq2000
-
isas: iq2000
Model variants
iq10 - IQ10 coprocessor
iq2000 - IQ2000 microprocessor
Registers
h-gr - General purpose registers
-
machines: base
-
bitsize: 32
-
array: [32]
names:
r0 |
0 |
%0 |
0 |
r1 |
1 |
%1 |
1 |
r2 |
2 |
%2 |
2 |
r3 |
3 |
%3 |
3 |
r4 |
4 |
%4 |
4 |
r5 |
5 |
%5 |
5 |
r6 |
6 |
%6 |
6 |
r7 |
7 |
%7 |
7 |
r8 |
8 |
%8 |
8 |
r9 |
9 |
%9 |
9 |
r10 |
10 |
%10 |
10 |
r11 |
11 |
%11 |
11 |
r12 |
12 |
%12 |
12 |
r13 |
13 |
%13 |
13 |
r14 |
14 |
%14 |
14 |
r15 |
15 |
%15 |
15 |
r16 |
16 |
%16 |
16 |
r17 |
17 |
%17 |
17 |
r18 |
18 |
%18 |
18 |
r19 |
19 |
%19 |
19 |
r20 |
20 |
%20 |
20 |
r21 |
21 |
%21 |
21 |
r22 |
22 |
%22 |
22 |
r23 |
23 |
%23 |
23 |
r24 |
24 |
%24 |
24 |
r25 |
25 |
%25 |
25 |
r26 |
26 |
%26 |
26 |
r27 |
27 |
%27 |
27 |
r28 |
28 |
%28 |
28 |
r29 |
29 |
%29 |
29 |
r30 |
30 |
%30 |
30 |
r31 |
31 |
%31 |
31 |
h-pc - program counter
-
machines: base
-
bitsize: 32
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
https://sourceware.org/cgen/