OR1K Architecture Documentation


DISCLAIMER: This documentation is derived from the cgen cpu description of this architecture, and does not represent official documentation of the chip maker.


In cgen-parlance, an architecture consists of machines and models. A `machine' is the specification of a variant of the architecture, and a `model' is the implementation of that specification. Typically there is a one-to-one correspondance between machine and model. The distinction allows for separation of what application programs see (the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code. Chip variants that are quite dissimilar can be treated separately by the generated code even though they're both members of the same architecture.

OR1K Architecture

This section describes various things about the cgen description of the OR1K architecture. Familiarity with cgen cpu descriptions is assumed.

Bit number orientation (arch.lsb0?): lsb = 0

ISA description

CPU Families

Machine variants

or32 - Generic OpenRISC 1000 32-bit CPU

or32nd - Generic OpenRISC 1000 32-bit CPU with no branch delay slot

or64 - Generic OpenRISC 1000 64-bit CPU

or64nd - Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot

Model variants

or1200 - OpenRISC 1200 model

or1200nd - OpenRISC 1200 model with no branch delay slot

Registers

h-atomic-address - atomic reserve address

h-atomic-reserve - atomic reserve flag

h-fd32r - or32 floating point registers (double, virtual)

h-fdr - or64 floating point registers (double, virtual)