SH Architecture Documentation

DISCLAIMER: This documentation is derived from the cgen cpu description of this architecture, and does not represent official documentation of the chip maker.

Architecture
Machine variants
Model variants
Registers
Instructions
Macro instructions
Assembler supplemental

In cgen-parlance, an architecture consists of machines and models. A `machine' is the specification of a variant of the architecture, and a `model' is the implementation of that specification. Typically there is a one-to-one correspondance between machine and model. The distinction allows for separation of what application programs see (the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code. Chip variants that are quite dissimilar can be treated separately by the generated code even though they're both members of the same architecture.

SH Architecture

This section describes various things about the cgen description of the SH architecture. Familiarity with cgen cpu descriptions is assumed.

Bit number orientation (arch.lsb0?): msb = 0

ISA description

compact - SHcompact 16/32 bit instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:
media - SHmedia 32-bit instruction set
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist:
- decode-splits:

CPU Families

sh64 - SH 64-bit family

Machines:
- sh2 - SH-2 CPU core
  
  Models:
  - sh2 - sh2 reference implementation
- sh2a-fpu - SH-2a CPU core with fpu
  
  Models:
  - sh2a-fpu - sh2a-fpu reference implementation
- sh2a-nofpu - SH-2a CPU core with no fpu
  
  Models:
  - sh2a-nofpu - sh2a-nofpu reference implementation
- sh2e - SH-2e CPU core
  
  Models:
  - sh2e - sh2e reference implementation
- sh3 - SH-3 CPU core
  
  Models:
  - sh3 - sh3 reference implementation
- sh3e - SH-3e CPU core
  
  Models:
  - sh3e - sh3e reference implementation
- sh4 - SH-4 CPU core with fpu
  
  Models:
  - sh4 - sh4 reference implementation
- sh4-nofpu - SH-4 CPU core - no fpu
  
  Models:
  - sh4-nofpu - sh4 nofpu reference implementation
- sh4a - SH-4a CPU core with fpu
  
  Models:
  - sh4a - sh4a reference implementation
- sh4a-nofpu - SH-4a CPU core - no fpu
  
  Models:
  - sh4a-nofpu - sh4a no fpu reference implementation
- sh4al - SH-4al CPU core
  
  Models:
  - sh4al - sh4al reference implementation
- sh5 - SH-5 CPU core
  
  Models:
  - sh5 - sh5 reference implementation
  - sh5-media - sh5 media reference implementation

sh2 - SH-2 CPU core

bfd-name: sh2
isas: compact

sh2a-fpu - SH-2a CPU core with fpu

bfd-name: sh2a-fpu
isas: compact

sh2a-nofpu - SH-2a CPU core with no fpu

bfd-name: sh2a-nofpu
isas: compact

sh2e - SH-2e CPU core

bfd-name: sh2e
isas: compact

sh3 - SH-3 CPU core

bfd-name: sh3
isas: compact

sh3e - SH-3e CPU core

bfd-name: sh3e
isas: compact

sh4 - SH-4 CPU core with fpu

bfd-name: sh4
isas: compact

sh4-nofpu - SH-4 CPU core - no fpu

bfd-name: sh4-nofpu
isas: compact

sh4a - SH-4a CPU core with fpu

bfd-name: sh4a
isas: compact

sh4a-nofpu - SH-4a CPU core - no fpu

bfd-name: sh4a-nofpu
isas: compact

sh4al - SH-4al CPU core

bfd-name: sh4al
isas: compact

sh5 - SH-5 CPU core

bfd-name: sh5
isas: compact media

Model variants

sh2 - sh2 reference implementation
sh2a-fpu - sh2a-fpu reference implementation
sh2a-nofpu - sh2a-nofpu reference implementation
sh2e - sh2e reference implementation
sh3 - sh3 reference implementation
sh3e - sh3e reference implementation
sh4 - sh4 reference implementation
sh4-nofpu - sh4 nofpu reference implementation
sh4a - sh4a reference implementation
sh4a-nofpu - sh4a no fpu reference implementation
sh4al - sh4al reference implementation
sh5 - sh5 reference implementation
sh5-media - sh5 media reference implementation

sh2 - sh2 reference implementation

sh2a-fpu - sh2a-fpu reference implementation

sh2a-nofpu - sh2a-nofpu reference implementation

sh2e - sh2e reference implementation

sh3 - sh3 reference implementation

sh3e - sh3e reference implementation

sh4 - sh4 reference implementation

sh4-nofpu - sh4 nofpu reference implementation

sh4a - sh4a reference implementation

sh4a-nofpu - sh4a no fpu reference implementation

sh4al - sh4al reference implementation

sh5 - sh5 reference implementation

sh5-media - sh5 media reference implementation

Registers

h-cr - Control registers
h-dr - Double precision floating point registers
h-drc - Double precision floating point registers
h-endian - Current endian mode
h-fmov - floating point registers for fmov
h-fmtx - Single precision floating point matrices
h-fp - Single precision floating point register pairs
h-fpscr - Floating point status and control register
h-fr - Single precision floating point registers
h-frbit - Floating point register file bit
h-frc - Single precision floating point registers
h-fsd - Single/Double precision floating point registers
h-fv - Single precision floating point vectors
h-fvc - Single precision floating point vectors
h-gbr - Global base register
h-gr - General purpose integer registers
h-grc - General purpose integer registers (SHcompact view)
h-ism - Current instruction set mode
h-mach - Multiply-accumulate high register
h-macl - Multiple-accumulate low register
h-mbit - Divide-step M flag
h-pc - Program counter
h-pr - Procedure link register
h-prbit - Floating point precision bit
h-qbit - Divide-step Q flag
h-sbit - Multiply-accumulate saturation flag
h-sr - Status register
h-szbit - Floating point transfer size bit
h-tbit - Condition code flag
h-tr - Branch target registers
h-vbr - Vector base register
h-xd - Extended double precision floating point registers
h-xf - Extended single precision floating point registers

h-cr - Control registers

machines: base
bitsize: 64

array: [64]
names:

h-dr - Double precision floating point registers

machines: base
bitsize: 64
array: [64]
names:

cr0	0
cr1	1
cr2	2
cr3	3
cr4	4
cr5	5
cr6	6
cr7	7
cr8	8
cr9	9
cr10	10
cr11	11
cr12	12
cr13	13
cr14	14
cr15	15
cr16	16
cr17	17
cr18	18
cr19	19
cr20	20
cr21	21
cr22	22
cr23	23
cr24	24
cr25	25
cr26	26
cr27	27
cr28	28
cr29	29
cr30	30
cr31	31
cr32	32
cr33	33
cr34	34
cr35	35
cr36	36
cr37	37
cr38	38
cr39	39
cr40	40
cr41	41
cr42	42
cr43	43
cr44	44
cr45	45
cr46	46
cr47	47
cr48	48
cr49	49
cr50	50
cr51	51
cr52	52
cr53	53
cr54	54
cr55	55
cr56	56
cr57	57
cr58	58
cr59	59
cr60	60
cr61	61
cr62	62
cr63	63

h-drc - Double precision floating point registers

machines: base
bitsize: 64
array: [8]
names:

dr0	0
dr2	2
dr4	4
dr6	6
dr8	8
dr10	10
dr12	12
dr14	14
dr16	16
dr18	18
dr20	20
dr22	22
dr24	24
dr26	26
dr28	28
dr30	30
dr32	32
dr34	34
dr36	36
dr38	38
dr40	40
dr42	42
dr44	44
dr46	46
dr48	48
dr50	50
dr52	52
dr54	54
dr56	56
dr58	58
dr60	60
dr62	62

h-endian - Current endian mode

machines: base
bitsize: 1

h-fmov - floating point registers for fmov

machines: sh2e sh2a-fpu sh3e sh4 sh4a sh5
bitsize: 64
array: [16]
names:

dr0	0
dr2	2
dr4	4
dr6	6
dr8	8
dr10	10
dr12	12
dr14	14

h-fmtx - Single precision floating point matrices

machines: base
bitsize: 32
array: [64]
names:

fr0	0
fr1	1
fr2	2
fr3	3
fr4	4
fr5	5
fr6	6
fr7	7
fr8	8
fr9	9
fr10	10
fr11	11
fr12	12
fr13	13
fr14	14
fr15	15

h-fp - Single precision floating point register pairs

machines: base
bitsize: 32
array: [64]
names:

mtrx0	0
mtrx16	16
mtrx32	32
mtrx48	48

h-fpscr - Floating point status and control register

machines: base
bitsize: 32

h-fr - Single precision floating point registers

machines: base
bitsize: 32
array: [64]
names:

fp0	0
fp2	2
fp4	4
fp6	6
fp8	8
fp10	10
fp12	12
fp14	14
fp16	16
fp18	18
fp20	20
fp22	22
fp24	24
fp26	26
fp28	28
fp30	30
fp32	32
fp34	34
fp36	36
fp38	38
fp40	40
fp42	42
fp44	44
fp46	46
fp48	48
fp50	50
fp52	52
fp54	54
fp56	56
fp58	58
fp60	60
fp62	62

h-frbit - Floating point register file bit

machines: base
bitsize: 1

h-frc - Single precision floating point registers

machines: base
bitsize: 32
array: [16]
names:

fr0	0
fr1	1
fr2	2
fr3	3
fr4	4
fr5	5
fr6	6
fr7	7
fr8	8
fr9	9
fr10	10
fr11	11
fr12	12
fr13	13
fr14	14
fr15	15
fr16	16
fr17	17
fr18	18
fr19	19
fr20	20
fr21	21
fr22	22
fr23	23
fr24	24
fr25	25
fr26	26
fr27	27
fr28	28
fr29	29
fr30	30
fr31	31
fr32	32
fr33	33
fr34	34
fr35	35
fr36	36
fr37	37
fr38	38
fr39	39
fr40	40
fr41	41
fr42	42
fr43	43
fr44	44
fr45	45
fr46	46
fr47	47
fr48	48
fr49	49
fr50	50
fr51	51
fr52	52
fr53	53
fr54	54
fr55	55
fr56	56
fr57	57
fr58	58
fr59	59
fr60	60
fr61	61
fr62	62
fr63	63

h-fsd - Single/Double precision floating point registers

machines: sh2e sh2a-fpu sh3e sh4 sh4a sh5
bitsize: 64
array: [16]
names:

fr0	0
fr1	1
fr2	2
fr3	3
fr4	4
fr5	5
fr6	6
fr7	7
fr8	8
fr9	9
fr10	10
fr11	11
fr12	12
fr13	13
fr14	14
fr15	15

h-fv - Single precision floating point vectors

machines: base
bitsize: 32
array: [64]
names:

fr0	0
fr1	1
fr2	2
fr3	3
fr4	4
fr5	5
fr6	6
fr7	7
fr8	8
fr9	9
fr10	10
fr11	11
fr12	12
fr13	13
fr14	14
fr15	15

h-fvc - Single precision floating point vectors

machines: base
bitsize: 32
array: [4]
names:

fv0	0
fv4	4
fv8	8
fv12	12
fv16	16
fv20	20
fv24	24
fv28	28
fv32	32
fv36	36
fv40	40
fv44	44
fv48	48
fv52	52
fv56	56
fv60	60

h-gbr - Global base register

machines: base
bitsize: 32

h-gr - General purpose integer registers

machines: base
bitsize: 64
array: [64]
names:

fv0	0
fv4	4
fv8	8
fv12	12

h-grc - General purpose integer registers (SHcompact view)

machines: base
bitsize: 32
array: [16]
names:

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15
r16	16
r17	17
r18	18
r19	19
r20	20
r21	21
r22	22
r23	23
r24	24
r25	25
r26	26
r27	27
r28	28
r29	29
r30	30
r31	31
r32	32
r33	33
r34	34
r35	35
r36	36
r37	37
r38	38
r39	39
r40	40
r41	41
r42	42
r43	43
r44	44
r45	45
r46	46
r47	47
r48	48
r49	49
r50	50
r51	51
r52	52
r53	53
r54	54
r55	55
r56	56
r57	57
r58	58
r59	59
r60	60
r61	61
r62	62
r63	63

h-ism - Current instruction set mode

machines: base
bitsize: 1

h-mach - Multiply-accumulate high register

machines: base
bitsize: 32

h-macl - Multiple-accumulate low register

machines: base
bitsize: 32

h-mbit - Divide-step M flag

machines: base
bitsize: 1

h-pc - Program counter

machines: base
bitsize: 64

h-pr - Procedure link register

machines: base
bitsize: 32

h-prbit - Floating point precision bit

machines: base
bitsize: 1

h-qbit - Divide-step Q flag

machines: base
bitsize: 1

h-sbit - Multiply-accumulate saturation flag

machines: base
bitsize: 1

h-sr - Status register

machines: base
bitsize: 32

h-szbit - Floating point transfer size bit

machines: base
bitsize: 1

h-tbit - Condition code flag

machines: base
bitsize: 1

h-tr - Branch target registers

machines: base
bitsize: 64
array: [8]
names:

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15

h-vbr - Vector base register

machines: base
bitsize: 32

h-xd - Extended double precision floating point registers

machines: base
bitsize: 64
array: [8]
names:

tr0	0
tr1	1
tr2	2
tr3	3
tr4	4
tr5	5
tr6	6
tr7	7

h-xf - Extended single precision floating point registers

machines: base
bitsize: 32
array: [16]
names:

fr0	0
fr1	1
fr2	2
fr3	3
fr4	4
fr5	5
fr6	6
fr7	7
fr8	8
fr9	9
fr10	10
fr11	11
fr12	12
fr13	13
fr14	14
fr15	15

Assembler supplemental

This documentation was machine generated from the cgen cpu description files for this architecture.
https://sourceware.org/cgen/

xf0	0
xf1	1
xf2	2
xf3	3
xf4	4
xf5	5
xf6	6
xf7	7
xf8	8
xf9	9
xf10	10
xf11	11
xf12	12
xf13	13
xf14	14
xf15	15

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15
r16	16
r17	17
r18	18
r19	19
r20	20
r21	21
r22	22
r23	23
r24	24
r25	25
r26	26
r27	27
r28	28
r29	29
r30	30
r31	31
r32	32
r33	33
r34	34
r35	35
r36	36
r37	37
r38	38
r39	39
r40	40
r41	41
r42	42
r43	43
r44	44
r45	45
r46	46
r47	47
r48	48
r49	49
r50	50
r51	51
r52	52
r53	53
r54	54
r55	55
r56	56
r57	57
r58	58
r59	59
r60	60
r61	61
r62	62
r63	63

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15
r16	16
r17	17
r18	18
r19	19
r20	20
r21	21
r22	22
r23	23
r24	24
r25	25
r26	26
r27	27
r28	28
r29	29
r30	30
r31	31
r32	32
r33	33
r34	34
r35	35
r36	36
r37	37
r38	38
r39	39
r40	40
r41	41
r42	42
r43	43
r44	44
r45	45
r46	46
r47	47
r48	48
r49	49
r50	50
r51	51
r52	52
r53	53
r54	54
r55	55
r56	56
r57	57
r58	58
r59	59
r60	60
r61	61
r62	62
r63	63

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15
r16	16
r17	17
r18	18
r19	19
r20	20
r21	21
r22	22
r23	23
r24	24
r25	25
r26	26
r27	27
r28	28
r29	29
r30	30
r31	31
r32	32
r33	33
r34	34
r35	35
r36	36
r37	37
r38	38
r39	39
r40	40
r41	41
r42	42
r43	43
r44	44
r45	45
r46	46
r47	47
r48	48
r49	49
r50	50
r51	51
r52	52
r53	53
r54	54
r55	55
r56	56
r57	57
r58	58
r59	59
r60	60
r61	61
r62	62
r63	63

r0	0
r1	1
r2	2
r3	3
r4	4
r5	5
r6	6
r7	7
r8	8
r9	9
r10	10
r11	11
r12	12
r13	13
r14	14
r15	15