SH Architecture Documentation

DISCLAIMER: This documentation is derived from the cgen cpu description of this architecture, and does not represent official documentation of the chip maker.

In cgen-parlance, an architecture consists of machines and models. A `machine' is the specification of a variant of the architecture, and a `model' is the implementation of that specification. Typically there is a one-to-one correspondance between machine and model. The distinction allows for separation of what application programs see (the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code. Chip variants that are quite dissimilar can be treated separately by the generated code even though they're both members of the same architecture.

SH Architecture

This section describes various things about the cgen description of the SH architecture. Familiarity with cgen cpu descriptions is assumed.

Bit number orientation (arch.lsb0?): msb = 0

ISA description

CPU Families

Machine variants

sh2 - SH-2 CPU core

sh2a-fpu - SH-2a CPU core with fpu

sh2a-nofpu - SH-2a CPU core with no fpu

sh2e - SH-2e CPU core

sh3 - SH-3 CPU core

sh3e - SH-3e CPU core

sh4 - SH-4 CPU core with fpu

sh4-nofpu - SH-4 CPU core - no fpu

sh4a - SH-4a CPU core with fpu

sh4a-nofpu - SH-4a CPU core - no fpu

sh4al - SH-4al CPU core

sh5 - SH-5 CPU core

Model variants

sh2 - sh2 reference implementation

sh2a-fpu - sh2a-fpu reference implementation

sh2a-nofpu - sh2a-nofpu reference implementation

sh2e - sh2e reference implementation

sh3 - sh3 reference implementation

sh3e - sh3e reference implementation

sh4 - sh4 reference implementation

sh4-nofpu - sh4 nofpu reference implementation

sh4a - sh4a reference implementation

sh4a-nofpu - sh4a no fpu reference implementation

sh4al - sh4al reference implementation

sh5 - sh5 reference implementation

sh5-media - sh5 media reference implementation


h-cr - Control registers